Closed ranvd closed 3 months ago
Got it. I will separate this PR into more pull requests, and leave this pull request with the actual implementation of preliminary SMP implementation .
In the commit log this time, I separate the commits of PLIC, CLINT implementation and LR/SC correction. Does it needed to create new PR for each individual commit?
In the commit log this time, I separate the commits of PLIC, CLINT implementation and LR/SC correction. Does it needed to create new PR for each individual commit?
You can gather them in one pull request, but you should utilize git rebase -i
to rework the commits, making them concise.
You can gather them in one pull request, but you should utilize
git rebase -i
to rework the commits, making them concise.
Sorry, I can't understand what exactly I should do. The current commit is already rebased to the latest master branch. Does "Rework the commits" mean I need to rewrite the commit message because my commit message is not clear enough to convey the idea of changes?
Does "Rework the commits" mean I need to rewrite the commit message because my commit message is not clear enough to convey the idea of changes?
The requested changes are involved in several functional and minimal commits which refer to their individual change lists. e.g.,
While the following changes should be amended into the above. e.g.,
Each commit should be fully traceable and well-understood.
I found that some implementations are not consistent with the specifications. I will update this branch afterward.
Can you integrate SMP aware tests in GitHub Actions?
Okay, I will integrate it by creating a new pull request afterward.
Thank @ranvd for contributing!
In this commit, semu is able to simulate SMP architecture running on the Linux kernel.
Before simulating SMP on semu, we need to enable SMP support in the Linux kernel. Please cross-compile the Linux kernel with the configuration file located at configs/linux.config.
After recompiling the Linux kernel with SMP support enabled, simply execute
make check SMP=1
to simulate a quad-hart RISC-V CPU.