thesps
commented
1 year ago Hi, I have a few comments/queries, hopefully we can get this working.
Have you been able to run one of the examples without issue? e.g. sklearn_to_hdl.py would be a good start for the HDL backend.
As well as the VHDL files produced, there will be some scripts for simulation and synthesis. Those can be a good starting point to jump from the conifer python to a Vivado project. There is support for GHDL simulation in conifer, you can access that by setting conifer.backends.vhdl.simulator = conifer.backends.vhdl.GHDL before starting conversion of the model. When you write/compile/build the project after that, a script ghdl_compile.sh will be written out. It's not so different from the one you posted, but there are some more flags for the libraries and VHDL 2008 setting.
I tried doing something like you described, adding ghdl --synth --work=BDT --std=08 --out=verilog BDT.BDTTop > BDTTop.v to the ghdl_compile.sh script, then fiddling the VHDL testbench BDTTestbench.vhd to instantiate the Verilog module, and run the whole thing from Vivado 2020.1. I also see only Xs for the output. I'll keep digging into it, but the unmodified workflow does work for running synthesis and simulation.
I do also see this AddReduce.vhd:28:11:warning: declaration of "addreduce" hides entity "addreduce" [-Whide] warning from GHDL. I will look into whether that's the issue.
Is there any reason to choose one backend over another for your project? It might be worth trying the HLS backend and exporting the C Synthesized model as Verilog if that's how you'll integrate it later.
SebastianHambura
Hi,
I've started working with this tool. I tried to convert a simple xgboost tree into VHDL. Conifer is creating the files without a problem, however when I try to import them in Vivado it's a mess. After struggling a bit with the library names (it's my first time using VHDL, usually I'm working with Verilog), I decide to go another route and convert the VHDL code into a Verilog module using GHDL (and/or Yosys).
In case someone is curious, that's how I'm currently doing it :
``` ghdl -a Constants.vhd ghdl -a Types.vhd ghdl -a AddReduce.vhd ghdl -a Arrays0.vhd ghdl -a Tree.vhd ghdl -a BDT.vhd ghdl -a BDTTop.vhd ghdl --synth --out=verilog bdttop > BDTTop.v ```
It's seems to be working, and while my VHDL attemps crashed Vivado, the Verilog file plays very nicely.
However I get following warnings :
And indeed, when I try to run a simulation with Vivado I find that the output signal from the tree is 'XXXXXXXX', and I have some internal ZZZs .
Is this an issue from your side, or did something go wrong during the translation process ?
(I'm using Vivado 2020.1)