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trabucayre / openFPGALoader

Universal utility for programming FPGA
https://trabucayre.github.io/openFPGALoader/
Apache License 2.0
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Attempting to Flash SPI PROM of a custom board - Dragon-L #460

Open AnantaSrikar opened 1 month ago

AnantaSrikar commented 1 month ago

I am attempting to flash a bitstream to a custom FPGA board, called the Dragon-L. It has a Spartan-6 XC6SLX25T-CSG324 FPGA on board. I am using an Altera USB Blaster as the JTAG adapter.

I have built and tried the latest openFPGALoader. Upon trying to flash a bitstream, I got the following error:

❯ openFPGALoader -c usb-blaster ledblink.bit
empty
JTAG init failed with: Unknown device with IDCODE: 0x24024093 (manufacturer: 0x049 (Xilinx), part: 0x20 vers: 0x2

Then, I did some research and figured out I could add my the IDCODE to src/part.hpp. I added the following and recompiled:

        {0x04004093, {"xilinx", "spartan6", "xc6slx25",        6}},
+       {0x24024093, {"xilinx", "spartan6", "xc6slx25T",       6}},
        {0x04008093, {"xilinx", "spartan6", "xc6slx45",        6}},

Then, I was able to flash to the SRAM of the FPGA with the following output:

❯ ./openFPGALoader -c usb-blaster ledblink.bit --verbose 
empty
found 1 devices
index 0:
    idcode 0x24024093
    manufacturer xilinx
    family spartan6
    model  xc6slx25T
    irlength 6
File type : bit
Open file DONE
Parse file DONE
bitstream header infos
date: 2024/05/22
design_name: ledblink.ncd
hour: 10:26:28
part_name: 6slx25tcsg324
toolVersion: 0xFFFFFFFF
userID: 0xFFFFFFFF
load program
Load SRAM: [==================================================] 100.00%
Done
Shift IR 35
ir: 1 isc_done 1 isc_ena 0 init 1 done 1

I wanted to take it a step ahead and see if I could flash the same onto the onboard SPI flash, and tried adding the -f flag, and errored out with the following output:

❯ ./openFPGALoader -c usb-blaster -f ledblink.bit --verbose
empty
write to flash
found 1 devices
index 0:
    idcode 0x24024093
    manufacturer xilinx
    family spartan6
    model  xc6slx25T
    irlength 6
File type : bit
Open file DONE
Parse file DONE
bitstream header infos
date: 2024/05/22
design_name: ledblink.ncd
hour: 10:26:28
part_name: 6slx25tcsg324
toolVersion: 0xFFFFFFFF
userID: 0xFFFFFFFF
Can't program SPI flash: missing device-package information

I did some more research and I figured out I could add the --fpga-part flag, and ran the same, but I still got an error:

❯ ./openFPGALoader -c usb-blaster --fpga-part xc6slx9csg324 -f ../../fpgaconf/captures/ledblink.bit --verbose
empty
write to flash
found 1 devices
index 0:
    idcode 0x24024093
    manufacturer xilinx
    family spartan6
    model  xc6slx25T
    irlength 6
File type : bit
Open file DONE
Parse file DONE
bitstream header infos
date: 2024/05/22
design_name: ledblink.ncd
hour: 10:26:28
part_name: 6slx25tcsg324
toolVersion: 0xFFFFFFFF
userID: 0xFFFFFFFF
use: /home/srikar/projects/dragon-l/openFPGALoader/spiOverJtag/spiOverJtag_xc6slx9csg324.bit.gz
load program
Load SRAM: [==================================================] 100.00%
Done
Shift IR 11
ir: 1 isc_done 0 isc_ena 0 init 1 done 0
Register raw value: 0x0
CRC Error      No CRC error
Part Secured   0
MMCM lock      0
DCI match      0
EOS            0
GTS CFG B      0
GWE            0
GHIGH B        0
MODE           0
INIT Complete  0
INIT B         0
Release Done   0
Done           0
ID Error       No ID error
DEC Error      0
XADC Over temp 0
STARTUP State  0
Reserved       0
BUS Width      x1
Reserved       0
cd 96 76 80 read cd967680
Detail: 
Jedec ID          : cd
memory type       : 96
memory capacity   : 76
RDSR : 68
WIP  : 0
WEL  : 0
BP   : a
TB   : 1
SRWD : 0
flash chip unknown: use basic protection detection
unlock blocks
Error: block protection is set
       can't unlock without --unprotect-flash

Since the error mentioned the flag --uprotect-flash, I tried that too, but still failed with a timeout error:

❯ ./openFPGALoader -c usb-blaster --fpga-part xc6slx9csg324 -f ../../fpgaconf/captures/ledblink.bit --unprotect-flash --verbose 
empty
write to flash
found 1 devices
index 0:
    idcode 0x24024093
    manufacturer xilinx
    family spartan6
    model  xc6slx25T
    irlength 6
File type : bit
Open file DONE
Parse file DONE
bitstream header infos
date: 2024/05/22
design_name: ledblink.ncd
hour: 10:26:28
part_name: 6slx25tcsg324
toolVersion: 0xFFFFFFFF
userID: 0xFFFFFFFF
use: /home/srikar/projects/dragon-l/openFPGALoader/spiOverJtag/spiOverJtag_xc6slx9csg324.bit.gz
load program
Load SRAM: [==================================================] 100.00%
Done
Shift IR 11
ir: 1 isc_done 0 isc_ena 0 init 1 done 0
Register raw value: 0x0
CRC Error      No CRC error
Part Secured   0
MMCM lock      0
DCI match      0
EOS            0
GTS CFG B      0
GWE            0
GHIGH B        0
MODE           0
INIT Complete  0
INIT B         0
Release Done   0
Done           0
ID Error       No ID error
DEC Error      0
XADC Over temp 0
STARTUP State  0
Reserved       0
BUS Width      x1
Reserved       0
ad b4 40 80 read adb44080
Detail: 
Jedec ID          : ad
memory type       : b4
memory capacity   : 40
RDSR : 2c
WIP  : 0
WEL  : 0
BP   : 3
TB   : 1
SRWD : 0
flash chip unknown: use basic protection detection
unlock blocks
timeout: ff ff ff
ff
wait: Error

I've double checked the pinout for the SPI PROM and it should be fine. I am not sure what I'm missing here, and I hope to make some changes and add official support to this board.

The flash chip in use is an 25P80VP by STMicroelectronics. I believe this is the datasheet for the same.

I'm not sure what I'm missing here, hope to find some insights and direction for the same. Thanks!

trabucayre commented 1 month ago

Yes. To be able to use openFPGALoader with a FPGA not already supported you have to update list of idcode (Yes, A better way is to import for some family all variants to avoid this type of issue).

But to update the flash with a bitstream you needs a sort of bridge (called spiOverJtag). For Xilinx you can't directly have access to the flash by using JTAG and you needs to load a gateware to interconnect these two interfaces. But unfortunately one bitstream is required by FPGA type (family, size, package), this why spiOverJtag directory contains a bunch of bitstreams. Here you have tried to load a bitstream dedicated to another model (size/model) this why openFPGALoader is unable to access FLASH chip.

For this step you have to follow approach similar to this commit

AnantaSrikar commented 1 month ago

Thank you so much for getting back to me. The way Xilinx accesses the SPI over JTAG is interesting. I will try looking around and getting the bitstream for xc6slx25tcsg324.bit.gz. I think it should be pretty straightforward after that. Any idea where I should be looking for the same?

AnantaSrikar commented 1 month ago

I figured out how to generate the bitstream:

trabucayre commented 1 month ago

Jedec ID seems wrong must be 0x2014. There is a problem with communication but I suspect the chip is in quad mode instead of SPI mode. But I must check if it's possible for your board. Maybe I have to order one, but it's a bit expensive.

trabucayre commented 1 month ago

In fact there is no schematics available... Could you also try with other JTAG cable? like ftdi?

AnantaSrikar commented 1 month ago

I'm not too sure about quad mode. I will also contact the board manufacturer to see if I can get more details and maybe the schematic. Regarding another JTAG cable, I'll have to order one.

Regarding another JTAG cable, do you think I can use this to program the FPGA? I've never worked with FPGAs before, so I'm a little unsure about how I should go ahead.

AnantaSrikar commented 1 month ago

I've contacted the Dragon-L board developer regarding the SPI pinout. I'm attaching the schematic for the same. The board does not support the quad mode.

image

trabucayre commented 1 month ago

any FTDI do the job, the only you have to check is the pin voltage: usually for a jtag probe, jtag pins are powered by a power pins from the board. Your schematics confirms constraints file pinout, it's weird openFPGALoader and spiOverJtag are perfectly compatible with spartan6...

AnantaSrikar commented 1 month ago

That is weird. I will try dirty JTAG on Bluepill, an ST-Link v2 clone and a Raspberry Pi pico to see if I can get it to work. In the event it doesn't, I will purchase this FTDI cable and try again.

In the meantime, is there any signal that you would want me to verify by using an oscilloscope?

trabucayre commented 1 month ago

I think the best way is I have a physical to a similar board. Its not always easy to see reasons why an issue like here.

AnantaSrikar commented 1 month ago

I flashed a Bluepill board I had lying around with the dirtyJtag firmware. The SRAM flashing works just fine, like the USB Blaster. It fails whenever I try to flash to SPI flash.

I'm starting to think this is because I'm not using all the JTAG pins. I'm only using the TCK, TDO, TDI, and TMS pins that can be easily connected by the 2.54 headers. The JTAG port uses a smaller form factor 14-pin connector, which I'm still on the hunt for.

I will try buying a smaller 14-pin connector and connecting the remaining pins (TRST and SRST) to see if it works. Either that or the generated bitfile is somehow not the right one.

Attaching a picture for your reference.

signal-2024-06-04-111123

trabucayre commented 1 month ago

Don't buy anything: it's not required. Tests with altera blaster and dirtyJTAG are enough: the problem isn't related to the cable...

AnantaSrikar commented 1 month ago

Oh okay. Do you think its because the spiOverJtag_xc6slx25tcsg324.bit.gz is not the correct bitfile, maybe due to the Xilinx version or something?

Pasting the output of python3 build.py xc6slx25tcsg324 for your reference

❯ export PATH=$PATH:/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64

❯ python3 build.py xc6slx25tcsg324                       
Successfully created the directory tmp_xc6slx25tcsg324 
xtclsh spiOverJtag.tcl
INFO:HDLCompiler:1845 - Analyzing Verilog file
   "/home/srikar/projects/dragon-l/openFPGALoader/spiOverJtag/xilinx_spiOverJtag
   .v" into library work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
INFO:TclTasksC:2116 - The automatic calculation of top has been turned-off.
   Please set the new top explicitly by running the "project set top" command.
   To re-calculate the new top automatically, set the "Auto Implementation Top"
   property to true.
xtclsh spiOverJtag_run.tcl spiOverJtag.xise
INFO:HDLCompiler:1845 - Analyzing Verilog file
   "/home/srikar/projects/dragon-l/openFPGALoader/spiOverJtag/xilinx_spiOverJtag
   .v" into library work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.

Started : "Synthesize - XST".
Running xst...
Command Line: xst -intstyle ise -ifn "/home/srikar/projects/dragon-l/openFPGALoader/spiOverJtag/tmp_xc6slx25tcsg324/spiOverJtag.xst" -ofn "/home/srikar/projects/dragon-l/openFPGALoader/spiOverJtag/tmp_xc6slx25tcsg324/spiOverJtag.syr"
Reading design: spiOverJtag.prj

=========================================================================
*                          HDL Parsing                                  *
=========================================================================
Analyzing Verilog file "/home/srikar/projects/dragon-l/openFPGALoader/spiOverJtag/xilinx_spiOverJtag.v" into library work
Parsing module <spiOverJtag>.

=========================================================================
*                            HDL Elaboration                            *
=========================================================================

Elaborating module <spiOverJtag>.

Elaborating module <BSCAN_SPARTAN6(JTAG_CHAIN=1)>.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <spiOverJtag>.
    Related source file is "/home/srikar/projects/dragon-l/openFPGALoader/spiOverJtag/xilinx_spiOverJtag.v".
    Found 1-bit register for signal <csn>.
    Summary:
    inferred   1 D-type flip-flop(s).
    inferred   1 Multiplexer(s).
Unit <spiOverJtag> synthesized.

=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                                            : 1
 1-bit register                                        : 1
# Multiplexers                                         : 1
 1-bit 2-to-1 multiplexer                              : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# Registers                                            : 1
 Flip-Flops                                            : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <spiOverJtag> ...

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block spiOverJtag, actual ratio is 0.

Final Macro Processing ...

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 1
 Flip-Flops                                            : 1

=========================================================================

=========================================================================
*                           Partition Report                            *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Design Summary                             *
=========================================================================

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
sck_OBUF                           | NONE(fsm_csn)          | 1     |
-----------------------------------+------------------------+-------+
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design

Timing Summary:
---------------
Speed Grade: -3

   Minimum period: No path found
   Minimum input arrival time before clock: 1.985ns
   Maximum output required time after clock: 3.597ns
   Maximum combinational path delay: 3.187ns

=========================================================================

Process "Synthesize - XST" completed successfully

Started : "Translate".
Running ngdbuild...
Command Line: ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc /home/srikar/projects/dragon-l/openFPGALoader/spiOverJtag/constr_xc6s_t_csg324.ucf -p xc6slx25t-csg324-3 spiOverJtag.ngc spiOverJtag.ngd

Command Line: /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/ngdbuild -intstyle
ise -dd _ngo -nt timestamp -uc
/home/srikar/projects/dragon-l/openFPGALoader/spiOverJtag/constr_xc6s_t_csg324.u
cf -p xc6slx25t-csg324-3 spiOverJtag.ngc spiOverJtag.ngd

Reading NGO file
"/home/srikar/projects/dragon-l/openFPGALoader/spiOverJtag/tmp_xc6slx25tcsg324/s
piOverJtag.ngc" ...
Gathering constraint information from source properties...
Done.

Annotating constraints to design from ucf file
"/home/srikar/projects/dragon-l/openFPGALoader/spiOverJtag/constr_xc6s_t_csg324.
ucf" ...
Resolving constraint associations...
Checking Constraint Associations...
Done...

Checking expanded design ...

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Writing NGD file "spiOverJtag.ngd" ...
Total REAL time to NGDBUILD completion:  1 sec
Total CPU time to NGDBUILD completion:   1 sec

Writing NGDBUILD log file "spiOverJtag.bld"...

NGDBUILD done.

Process "Translate" completed successfully

Started : "Map".
Running map...
Command Line: map -intstyle ise -p xc6slx25t-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -detail -ir off -pr off -lc off -power off -o spiOverJtag_map.ncd spiOverJtag.ngd spiOverJtag.pcf
Using target part "6slx25tcsg324-3".
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
   (.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 2 secs 
Total CPU  time at the beginning of Placer: 2 secs 

Phase 1.1  Initial Placement Analysis
Phase 1.1  Initial Placement Analysis (Checksum:2d6449dc) REAL time: 2 secs 

Phase 2.7  Design Feasibility Check
Phase 2.7  Design Feasibility Check (Checksum:2d6449dc) REAL time: 2 secs 

Phase 3.31  Local Placement Optimization
Phase 3.31  Local Placement Optimization (Checksum:d656dd77) REAL time: 2 secs 

Phase 4.2  Initial Placement for Architecture Specific Features
Phase 4.2  Initial Placement for Architecture Specific Features
(Checksum:d656dd77) REAL time: 2 secs 

Phase 5.36  Local Placement Optimization
Phase 5.36  Local Placement Optimization (Checksum:d656dd77) REAL time: 2 secs 

Phase 6.30  Global Clock Region Assignment
Phase 6.30  Global Clock Region Assignment (Checksum:d656dd77) REAL time: 2 secs 

Phase 7.3  Local Placement Optimization
Phase 7.3  Local Placement Optimization (Checksum:d656dd77) REAL time: 2 secs 

Phase 8.5  Local Placement Optimization
Phase 8.5  Local Placement Optimization (Checksum:d656dd77) REAL time: 2 secs 

Phase 9.8  Global Placement
..
..
Phase 9.8  Global Placement (Checksum:e414247b) REAL time: 2 secs 

Phase 10.5  Local Placement Optimization
Phase 10.5  Local Placement Optimization (Checksum:e414247b) REAL time: 2 secs 

Phase 11.18  Placement Optimization
Phase 11.18  Placement Optimization (Checksum:887b616b) REAL time: 2 secs 

Phase 12.5  Local Placement Optimization
Phase 12.5  Local Placement Optimization (Checksum:887b616b) REAL time: 2 secs 

Phase 13.34  Placement Validation
Phase 13.34  Placement Validation (Checksum:887b616b) REAL time: 2 secs 

Total REAL time to Placer completion: 2 secs 
Total CPU  time to Placer completion: 2 secs 
Running post-placement packing...
Writing output files...

Design Summary:
Number of errors:      0
Number of warnings:    0
Slice Logic Utilization:
  Number of Slice Registers:                     0 out of  30,064    0%
  Number of Slice LUTs:                          2 out of  15,032    1%
    Number used as logic:                        2 out of  15,032    1%
      Number using O6 output only:               1
      Number using O5 output only:               0
      Number using O5 and O6:                    1
      Number used as ROM:                        0
    Number used as Memory:                       0 out of   3,664    0%

Slice Logic Distribution:
  Number of occupied Slices:                     2 out of   3,758    1%
  Number of MUXCYs used:                         0 out of   7,516    0%
  Number of LUT Flip Flop pairs used:            2
    Number with an unused Flip Flop:             2 out of       2  100%
    Number with an unused LUT:                   0 out of       2    0%
    Number of fully used LUT-FF pairs:           0 out of       2    0%
    Number of slice register sites lost
      to control set restrictions:               0 out of  30,064    0%

  A LUT Flip Flop pair for this architecture represents one LUT paired with
  one Flip Flop within a slice.  A control set is a unique combination of
  clock, reset, set, and enable signals for a registered element.
  The Slice Logic Distribution report is not meaningful if the design is
  over-mapped for a non-slice resource or if Placement fails.

IO Utilization:
  Number of bonded IOBs:                         6 out of     190    3%
    Number of LOCed IOBs:                        6 out of       6  100%
    IOB Flip Flops:                              1

Specific Feature Utilization:
  Number of RAMB16BWERs:                         0 out of      52    0%
  Number of RAMB8BWERs:                          0 out of     104    0%
  Number of BUFIO2/BUFIO2_2CLKs:                 0 out of      32    0%
  Number of BUFIO2FB/BUFIO2FB_2CLKs:             0 out of      32    0%
  Number of BUFG/BUFGMUXs:                       0 out of      16    0%
  Number of DCM/DCM_CLKGENs:                     0 out of       4    0%
  Number of ILOGIC2/ISERDES2s:                   0 out of     272    0%
  Number of IODELAY2/IODRP2/IODRP2_MCBs:         0 out of     272    0%
  Number of OLOGIC2/OSERDES2s:                   1 out of     272    1%
    Number used as OLOGIC2s:                     1
    Number used as OSERDES2s:                    0
  Number of BSCANs:                              1 out of       4   25%
  Number of BUFHs:                               0 out of     160    0%
  Number of BUFPLLs:                             0 out of       8    0%
  Number of BUFPLL_MCBs:                         0 out of       4    0%
  Number of DSP48A1s:                            0 out of      38    0%
  Number of GTPA1_DUALs:                         0 out of       1    0%
  Number of ICAPs:                               0 out of       1    0%
  Number of MCBs:                                0 out of       2    0%
  Number of PCIE_A1s:                            0 out of       1    0%
  Number of PCILOGICSEs:                         0 out of       2    0%
  Number of PLL_ADVs:                            0 out of       2    0%
  Number of PMVs:                                0 out of       1    0%
  Number of STARTUPs:                            0 out of       1    0%
  Number of SUSPEND_SYNCs:                       0 out of       1    0%

Average Fanout of Non-Clock Nets:                1.10

Peak Memory Usage:  680 MB
Total REAL time to MAP completion:  2 secs 
Total CPU time to MAP completion:   2 secs 

Mapping completed.
See MAP report file "spiOverJtag_map.mrp" for details.

Process "Map" completed successfully

Started : "Place & Route".
Running par...
Command Line: par -w -intstyle ise -ol high -mt off spiOverJtag_map.ncd spiOverJtag.ncd spiOverJtag.pcf

Constraints file: spiOverJtag.pcf.
Loading device for application Rf_Device from file '6slx25t.nph' in environment /opt/Xilinx/14.7/ISE_DS/ISE/.
   "spiOverJtag" is an NCD, version 3.2, device xc6slx25t, package csg324, speed -3

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)

INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par
   -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all
   internal clocks in this design. Because there are not defined timing requirements, a timing score will not be
   reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock.
   Note: For the fastest runtime, set the effort level to "std".  For best performance, set the effort level to "high".

Device speed data version:  "PRODUCTION 1.23 2013-10-13".

Device Utilization Summary:

Slice Logic Utilization:
  Number of Slice Registers:                     0 out of  30,064    0%
  Number of Slice LUTs:                          2 out of  15,032    1%
    Number used as logic:                        2 out of  15,032    1%
      Number using O6 output only:               1
      Number using O5 output only:               0
      Number using O5 and O6:                    1
      Number used as ROM:                        0
    Number used as Memory:                       0 out of   3,664    0%

Slice Logic Distribution:
  Number of occupied Slices:                     2 out of   3,758    1%
  Number of MUXCYs used:                         0 out of   7,516    0%
  Number of LUT Flip Flop pairs used:            2
    Number with an unused Flip Flop:             2 out of       2  100%
    Number with an unused LUT:                   0 out of       2    0%
    Number of fully used LUT-FF pairs:           0 out of       2    0%
    Number of slice register sites lost
      to control set restrictions:               0 out of  30,064    0%

  A LUT Flip Flop pair for this architecture represents one LUT paired with
  one Flip Flop within a slice.  A control set is a unique combination of
  clock, reset, set, and enable signals for a registered element.
  The Slice Logic Distribution report is not meaningful if the design is
  over-mapped for a non-slice resource or if Placement fails.

IO Utilization:
  Number of bonded IOBs:                         6 out of     190    3%
    Number of LOCed IOBs:                        6 out of       6  100%
    IOB Flip Flops:                              1

Specific Feature Utilization:
  Number of RAMB16BWERs:                         0 out of      52    0%
  Number of RAMB8BWERs:                          0 out of     104    0%
  Number of BUFIO2/BUFIO2_2CLKs:                 0 out of      32    0%
  Number of BUFIO2FB/BUFIO2FB_2CLKs:             0 out of      32    0%
  Number of BUFG/BUFGMUXs:                       0 out of      16    0%
  Number of DCM/DCM_CLKGENs:                     0 out of       4    0%
  Number of ILOGIC2/ISERDES2s:                   0 out of     272    0%
  Number of IODELAY2/IODRP2/IODRP2_MCBs:         0 out of     272    0%
  Number of OLOGIC2/OSERDES2s:                   1 out of     272    1%
    Number used as OLOGIC2s:                     1
    Number used as OSERDES2s:                    0
  Number of BSCANs:                              1 out of       4   25%
  Number of BUFHs:                               0 out of     160    0%
  Number of BUFPLLs:                             0 out of       8    0%
  Number of BUFPLL_MCBs:                         0 out of       4    0%
  Number of DSP48A1s:                            0 out of      38    0%
  Number of GTPA1_DUALs:                         0 out of       1    0%
  Number of ICAPs:                               0 out of       1    0%
  Number of MCBs:                                0 out of       2    0%
  Number of PCIE_A1s:                            0 out of       1    0%
  Number of PCILOGICSEs:                         0 out of       2    0%
  Number of PLL_ADVs:                            0 out of       2    0%
  Number of PMVs:                                0 out of       1    0%
  Number of STARTUPs:                            0 out of       1    0%
  Number of SUSPEND_SYNCs:                       0 out of       1    0%

Overall effort level (-ol):   High 
Router effort level (-rl):    High 

Starting initial Timing Analysis.  REAL time: 1 secs 
Finished initial Timing Analysis.  REAL time: 1 secs 

Starting Router

Phase  1  : 17 unrouted;      REAL time: 2 secs 

Phase  2  : 15 unrouted;      REAL time: 2 secs 

Phase  3  : 1 unrouted;      REAL time: 2 secs 

Phase  4  : 1 unrouted; (Par is working to improve performance)     REAL time: 2 secs 

Updating file: spiOverJtag.ncd with current fully routed design.

Phase  5  : 0 unrouted; (Par is working to improve performance)     REAL time: 2 secs 

Phase  6  : 0 unrouted; (Par is working to improve performance)     REAL time: 2 secs 

Phase  7  : 0 unrouted; (Par is working to improve performance)     REAL time: 2 secs 

Phase  8  : 0 unrouted; (Par is working to improve performance)     REAL time: 2 secs 

Phase  9  : 0 unrouted; (Par is working to improve performance)     REAL time: 2 secs 

Phase 10  : 0 unrouted; (Par is working to improve performance)     REAL time: 2 secs 
Total REAL time to Router completion: 2 secs 
Total CPU time to Router completion: 2 secs 

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

Generating "PAR" statistics.
INFO:Par:459 - The Clock Report is not displayed in the non timing-driven mode.
Timing Score: 0 (Setup: 0, Hold: 0)

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

------------------------------------------------------------------------------------------------------
  Constraint                                | Requested  | Actual     | Logic  | Absolute   |Number of
                                            |            |            | Levels | Slack      |errors   
------------------------------------------------------------------------------------------------------

All constraints were met.

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 2 secs 
Total CPU time to PAR completion: 2 secs 

Peak Memory Usage:  626 MB

Placer: Placement generated during map.
Routing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 0
Number of info messages: 2

Writing design to file spiOverJtag.ncd

PAR done!

Process "Place & Route" completed successfully

Started : "Generate Post-Place & Route Static Timing".
Running trce...
Command Line: trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml spiOverJtag.twx spiOverJtag.ncd -o spiOverJtag.twr spiOverJtag.pcf
Loading device for application Rf_Device from file '6slx25t.nph' in environment
/opt/Xilinx/14.7/ISE_DS/ISE/.
   "spiOverJtag" is an NCD, version 3.2, device xc6slx25t, package csg324, speed
-3

Analysis completed Tue Jun  4 12:39:53 2024
--------------------------------------------------------------------------------

Generating Report ...

Number of warnings: 0
Total time: 1 secs 

Process "Generate Post-Place & Route Static Timing" completed successfully

Started : "Generate Programming File".
Running bitgen...
Command Line: bitgen -intstyle ise -f spiOverJtag.ut spiOverJtag.ncd

Process "Generate Programming File" completed successfully
INFO:TclTasksC:1850 - process run : Generate Programming File is done.
trabucayre commented 1 month ago

I must admit its hard to said. Flow looks good and your constraints file too... Maybe trying to disable flash at powerup time using a wire between CS and VCC to have an empty FPGA (flash be reserved by gateware loaded at boot time).

AnantaSrikar commented 3 weeks ago

I will try disabling the flash as the FPGA powers up and let you know how that works.

Besides that, I've had success flashing the SPI of the FPGA using the KNJN USBFX2-JTAG development board and the KNJN JTAG cable along with the FPGAconf portable executable. That exe application allows me to select the bitfile I want to flash, and click on flash boot for it to write it to SPI. So what I can also try writing the SpiOverJtag.bit to the flash and see how openFPGALoader works with that.