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tree-sitter / tree-sitter-verilog

SystemVerilog grammar for tree-sitter
MIT License
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Parsing error when elements of arrays occur in concatenations #68

Closed YikeZhou closed 1 year ago

YikeZhou commented 1 year ago

Given this:

module top;
  wire w [0:1];
  wire o;
  assign o = {w[1]};
endmodule

Run tree-sitter like this:

tree-sitter parse top.v

Got this output:

(source_file [0, 0] - [5, 0]
  (module_declaration [0, 0] - [4, 9]
    (module_header [0, 0] - [0, 10]
      (module_keyword [0, 0] - [0, 6])
      (simple_identifier [0, 7] - [0, 10]))
    (module_or_generate_item [1, 2] - [1, 15]
      (package_or_generate_item_declaration [1, 2] - [1, 15]
        (net_declaration [1, 2] - [1, 15]
          (net_type [1, 2] - [1, 6])
          (list_of_net_decl_assignments [1, 7] - [1, 14]
            (net_decl_assignment [1, 7] - [1, 14]
              (simple_identifier [1, 7] - [1, 8])
              (unpacked_dimension [1, 9] - [1, 14]
                (constant_range [1, 10] - [1, 13]
                  (constant_expression [1, 10] - [1, 11]
                    (constant_primary [1, 10] - [1, 11]
                      (primary_literal [1, 10] - [1, 11]
                        (integral_number [1, 10] - [1, 11]
                          (decimal_number [1, 10] - [1, 11]
                            (unsigned_number [1, 10] - [1, 11]))))))
                  (constant_expression [1, 12] - [1, 13]
                    (constant_primary [1, 12] - [1, 13]
                      (primary_literal [1, 12] - [1, 13]
                        (integral_number [1, 12] - [1, 13]
                          (decimal_number [1, 12] - [1, 13]
                            (unsigned_number [1, 12] - [1, 13])))))))))))))
    (module_or_generate_item [2, 2] - [2, 9]
      (package_or_generate_item_declaration [2, 2] - [2, 9]
        (net_declaration [2, 2] - [2, 9]
          (net_type [2, 2] - [2, 6])
          (list_of_net_decl_assignments [2, 7] - [2, 8]
            (net_decl_assignment [2, 7] - [2, 8]
              (simple_identifier [2, 7] - [2, 8]))))))
    (module_or_generate_item [3, 2] - [3, 20]
      (continuous_assign [3, 2] - [3, 20]
        (list_of_net_assignments [3, 9] - [3, 19]
          (net_assignment [3, 9] - [3, 19]
            (net_lvalue [3, 9] - [3, 10]
              (simple_identifier [3, 9] - [3, 10]))
            (expression [3, 13] - [3, 19]
              (inc_or_dec_expression [3, 13] - [3, 19] ■ should be "concatenation"
                (variable_lvalue [3, 13] - [3, 19]
                  (variable_lvalue [3, 14] - [3, 18]
                    (simple_identifier [3, 14] - [3, 15])
                    (select1 [3, 15] - [3, 18]
                      (bit_select1 [3, 15] - [3, 18]
                        (expression [3, 16] - [3, 17]
                          (primary [3, 16] - [3, 17]
                            (primary_literal [3, 16] - [3, 17]
                              (integral_number [3, 16] - [3, 17]
                                (decimal_number [3, 16] - [3, 17]
                                  (unsigned_number [3, 16] - [3, 17]))))))))))
                (inc_or_dec_operator [3, 19] - [3, 19])))))))))
top.v   0 ms    (MISSING "++" [3, 19] - [3, 19])
YikeZhou commented 1 year ago

I found a relevant comment here: https://github.com/tree-sitter/tree-sitter-verilog/issues/54#issuecomment-1625683001

In that case, b[0] is considered to be bit_select.

module mod ();
  assign a = {b[0]};
endmodule

This does remind me that I'm working with a parser, who cannot tell the difference between bit selection and element selection. Therefore, this issue is just a duplicate of #54.