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ucb-bar / chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
https://chipyard.readthedocs.io/en/stable/
BSD 3-Clause "New" or "Revised" License
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assertion failed: The Chisel compiler plugin is now required for compiling Chisel code while compiling vcu118 bringup #1190

Open logosAllen opened 2 years ago

logosAllen commented 2 years ago

Background Work

Chipyard Version and Hash

Release: 1.7.0 Hash: 4a11896

OS Setup

Ex: Output of uname -a and lsb_release -a

Linux LAPTOP-_ 5.10.102.1-microsoft-standard-WSL2 #1 SMP Wed Mar 2 00:30:59 UTC 2022 x86_64 x86_64 x86_64 GNU/Linux

No LSB modules are available. Distributor ID: Ubuntu Description: Ubuntu 20.04.4 LTS Release: 20.04 Codename: focal

Other Setup

Ex: Prior steps taken / Documentation Followed / etc...

./scripts/ubuntu-req.sh ./scripts/init-submodules-no-riscv-tools.sh ./scripts/build-toolchains.sh riscv-tools source env.sh ./scripts/init-fpga.sh cd fpga make SUB_PROJECT=bringup bitstream

Current Behavior

buildTopClockGenerator Frequency Summary Input Reference Frequency: 100.0 MHz Output clock subsystem_sbus_0, requested: 100.0 MHz, actual: 100.0 MHz (division of 1) Output clock subsystem_sbus_1, requested: 100.0 MHz, actual: 100.0 MHz (division of 1) Output clock subsystem_pbus_0, requested: 100.0 MHz, actual: 100.0 MHz (division of 1) Output clock subsystem_fbus_0, requested: 100.0 MHz, actual: 100.0 MHz (division of 1) Output clock subsystem_mbus_0, requested: 100.0 MHz, actual: 100.0 MHz (division of 1) Output clock subsystem_cbus_0, requested: 100.0 MHz, actual: 100.0 MHz (division of 1) Output clock implicit_clock, requested: 100.0 MHz, actual: 100.0 MHz (division of 1) mem AXI4-ID <= TL-Source mapping: [0, 10) <= [0, 10) "L2 InclusiveCache"

mem AXI4-ID <= TL-Source mapping: [0, 1) <= [ 0, 512) "TLFragmenter" [FIFO]

[error] (run-main-0) java.lang.AssertionError: assertion failed: The Chisel compiler plugin is now required for compiling Chisel code. Please see https://github.com/chipsalliance/chisel3#build-your-own-chisel-projects. [error] java.lang.AssertionError: assertion failed: The Chisel compiler plugin is now required for compiling Chisel code. Please see https://github.com/chipsalliance/chisel3#build-your-own-chisel-projects. [error] at ... () [error] at chipyard.fpga.vcu118.DDR2VCU118PlacedOverlay$$anon$1.(CustomOverlays.scala:49) [error] at chipyard.fpga.vcu118.DDR2VCU118PlacedOverlay.$anonfun$migClkRstNode$1(CustomOverlays.scala:49) [error] at freechips.rocketchip.diplomacy.BundleBridgeImp.$anonfun$bundle$3(BundleBridge.scala:24) [error] at scala.Option.map(Option.scala:230) [error] at freechips.rocketchip.diplomacy.BundleBridgeImp.$anonfun$bundle$2(BundleBridge.scala:24) [error] at chisel3.internal.prefix$.apply(prefix.scala:48) [error] at freechips.rocketchip.diplomacy.BundleBridgeImp.$anonfun$bundle$1(BundleBridge.scala:24) [error] at chisel3.internal.plugin.package$.autoNameRecursively(package.scala:33) [error] at freechips.rocketchip.diplomacy.BundleBridgeImp.bundle(BundleBridge.scala:24) [error] at freechips.rocketchip.diplomacy.BundleBridgeImp.bundle(BundleBridge.scala:20) [error] at freechips.rocketchip.diplomacy.SimpleNodeImp.bundleO(Nodes.scala:186) [error] at freechips.rocketchip.diplomacy.MixedNode.$anonfun$bundleOut$3(Nodes.scala:1207) [error] at scala.collection.TraversableLike.$anonfun$map$1(TraversableLike.scala:238) [error] at scala.collection.immutable.List.foreach(List.scala:392) [error] at scala.collection.TraversableLike.map(TraversableLike.scala:238) [error] at scala.collection.TraversableLike.map$(TraversableLike.scala:231) [error] at scala.collection.immutable.List.map(List.scala:298) [error] at freechips.rocketchip.diplomacy.MixedNode.$anonfun$bundleOut$2(Nodes.scala:1207) [error] at chisel3.internal.prefix$.apply(prefix.scala:48) [error] at freechips.rocketchip.diplomacy.MixedNode.$anonfun$bundleOut$1(Nodes.scala:1207) [error] at chisel3.internal.plugin.package$.autoNameRecursively(package.scala:33) [error] at freechips.rocketchip.diplomacy.MixedNode.bundleOut$lzycompute(Nodes.scala:1207) [error] at freechips.rocketchip.diplomacy.MixedNode.bundleOut(Nodes.scala:1207) [error] at freechips.rocketchip.diplomacy.MixedNode.$anonfun$danglesOut$1(Nodes.scala:1219) [error] at scala.collection.TraversableLike.$anonfun$map$1(TraversableLike.scala:238) [error] at scala.collection.immutable.List.foreach(List.scala:392) [error] at scala.collection.TraversableLike.map(TraversableLike.scala:238) [error] at scala.collection.immutable.List.foreach(List.scala:392) [error] at scala.collection.TraversableLike.map(TraversableLike.scala:238) [error] at scala.collection.TraversableLike.map$(TraversableLike.scala:231) [error] at scala.collection.immutable.List.map(List.scala:298) [error] at freechips.rocketchip.diplomacy.MixedNode.danglesOut(Nodes.scala:1213) [error] at freechips.rocketchip.diplomacy.MixedNode.instantiate(Nodes.scala:1267) [error] at freechips.rocketchip.diplomacy.LazyModuleImpLike.$anonfun$instantiate$4(LazyModule.scala:284) [error] at scala.collection.immutable.List.flatMap(List.scala:338) [error] at freechips.rocketchip.diplomacy.LazyModuleImpLike.instantiate(LazyModule.scala:284) [error] at freechips.rocketchip.diplomacy.LazyModuleImpLike.instantiate$(LazyModule.scala:273) [error] at freechips.rocketchip.diplomacy.LazyRawModuleImp.instantiate(LazyModule.scala:344) [error] at freechips.rocketchip.diplomacy.LazyRawModuleImp.$anonfun$x$22$2(LazyModule.scala:357) [error] at chisel3.withClockAndReset$.apply(MultiClock.scala:26) [error] at freechips.rocketchip.diplomacy.LazyRawModuleImp.$anonfun$x$22$1(LazyModule.scala:357) [error] at chisel3.internal.plugin.package$.autoNameRecursivelyProduct(package.scala:48) [error] at freechips.rocketchip.diplomacy.LazyRawModuleImp.(LazyModule.scala:356) [error] at chipyard.fpga.vcu118.VCU118FPGATestHarnessImp.(TestHarness.scala:96) [error] at chipyard.fpga.vcu118.bringup.BringupVCU118FPGATestHarnessImp.(TestHarness.scala:98) [error] at chipyard.fpga.vcu118.bringup.BringupVCU118FPGATestHarness.module$lzycompute(TestHarness.scala:95) [error] at chipyard.fpga.vcu118.bringup.BringupVCU118FPGATestHarness.module(TestHarness.scala:95) [error] at chipyard.fpga.vcu118.bringup.BringupVCU118FPGATestHarness.module(TestHarness.scala:26) [error] at freechips.rocketchip.stage.phases.PreElaboration.$anonfun$transform$1(PreElaboration.scala:38) [error] at ... () [error] at ... (Stack trace trimmed to user code only. Rerun with --full-stacktrace to see the full stack trace) [error] stack trace is suppressed; run last Compile / bgRunMain for the full output [error] Nonzero exit code: 1 [error] (Compile / runMain) Nonzero exit code: 1 [error] Total time: 50 s, completed Jun 23, 2022, 1:56:31 PM

Expected Behavior

should pass chisel compile and step into vivado process

Other Information

No response

logosAllen commented 2 years ago

I successfully built the bringup with modification of build.sbt.

lazy val fpga_platforms = (project in file("./fpga")) .dependsOn(chipyard, fpga_shells) +) .settings(chiselSettings) .settings(commonSettings)

jerryz123 commented 2 years ago

Can you submit a PR for this?