Correct initialization in LaneCtrl

ucb-bar / hwacha

Microarchitecture implementation of the decoupled vector-fetch accelerator

http://hwacha.org/

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Correct initialization in LaneCtrl #10

Open donggyukim opened 5 years ago

donggyukim commented 5 years ago

This seems to be necessary.

colinschmidt commented 5 years ago

How long did you hold reset? Pipelined reset in Hwacha is a bit longer than in Rocket.

donggyukim commented 5 years ago

5 cycles. But, I believe this is due to: https://github.com/ucb-bar/hwacha/blob/master/src/main/scala/lane-ctrl.scala#L66

If its value is greater than nSlices, it'll unexpectedly fire.

I actually got this assertion at the beginning of simulation:

Assertion failed: check sreg sched logic vqu_0
    at lane.scala:184 assert(!uop.valid || !uop.bits.sreg(i) || ctrl.io.uop.sreg(ri).valid, "check sreg sched logic "+name+"_"+i)