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ultraembedded / core_sdram_axi4

SDRAM controller with AXI4 interface
GNU General Public License v3.0
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port mapping the top module with AXI ip #2

Closed Madesh12 closed 4 years ago

Madesh12 commented 4 years ago

We are using sdram in our FPGA board. Our SDRAM same that you have given project. So I am working with your code. I want to create axi ip from your code and use it with the microblaze. I cannot port map Some signals in the top module with AXI4 peripheral in the creation of AXI ip. I gave the picture that I have stucked.

ultraembedded commented 4 years ago

It looks like you are connecting an AXI4-Lite interface to a full AXI-4 target, so you need to tie off the following inputs;

AWID = 0 // X AWBURST= 1 // INCR AWLEN = 0 // SINGLE WLAST = 1 // SINGLE ARID = 0 // X ARBURST = 1 // INCR ARLEN = 0 // SINGLE

Madesh12 commented 4 years ago

I have created the IP using your code. I just created the simple microblaze design with SDRAM. while running the design I regularly getting multiple driver nets error(screenshots added here). Please share your knowledge

On Tue, Oct 20, 2020 at 3:27 PM ultraembedded notifications@github.com wrote:

Closed #2 https://github.com/ultraembedded/core_sdram_axi4/issues/2.

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Madesh12 commented 4 years ago

On Thu, Oct 29, 2020 at 10:12 AM Techie zone madeshwaran8696@gmail.com wrote:

I have created the IP using your code. I just created the simple microblaze design with SDRAM. while running the design I regularly getting multiple driver nets error(screenshots added here). Please share your knowledge

On Tue, Oct 20, 2020 at 3:27 PM ultraembedded notifications@github.com wrote:

Closed #2 https://github.com/ultraembedded/core_sdram_axi4/issues/2.

— You are receiving this because you authored the thread. Reply to this email directly, view it on GitHub https://github.com/ultraembedded/core_sdram_axi4/issues/2#event-3897762297, or unsubscribe https://github.com/notifications/unsubscribe-auth/ALC6KZXKQX2FCU6G5WEAIATSLVNGZANCNFSM4SX5TO5A .

Madesh12 commented 4 years ago

This is my microblaze design with SDRAM

On Thu, Oct 29, 2020 at 10:12 AM Techie zone madeshwaran8696@gmail.com wrote:

On Thu, Oct 29, 2020 at 10:12 AM Techie zone madeshwaran8696@gmail.com wrote:

I have created the IP using your code. I just created the simple microblaze design with SDRAM. while running the design I regularly getting multiple driver nets error(screenshots added here). Please share your knowledge

On Tue, Oct 20, 2020 at 3:27 PM ultraembedded notifications@github.com wrote:

Closed #2 https://github.com/ultraembedded/core_sdram_axi4/issues/2.

— You are receiving this because you authored the thread. Reply to this email directly, view it on GitHub https://github.com/ultraembedded/core_sdram_axi4/issues/2#event-3897762297, or unsubscribe https://github.com/notifications/unsubscribe-auth/ALC6KZXKQX2FCU6G5WEAIATSLVNGZANCNFSM4SX5TO5A .

ultraembedded commented 4 years ago

I don’t see any screenshot.

Madesh12 commented 4 years ago

these are all the screenshots

On Thu, Oct 29, 2020 at 2:18 PM ultraembedded notifications@github.com wrote:

I don’t see any screenshot.

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ultraembedded commented 4 years ago

They are not showing up.

Madesh12 commented 4 years ago

please visit link to see the images https://ibb.co/GpyjjB4 https://ibb.co/djKTd4n

On Thu, Oct 29, 2020 at 3:18 PM ultraembedded notifications@github.com wrote:

They are not showing up.

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