No Module name 'prettytable'

verilog-to-routing / vtr-verilog-to-routing

Verilog to Routing -- Open Source CAD Flow for FPGA Research

https://verilogtorouting.org

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No Module name 'prettytable' #1920

Closed suyang5 closed 2 years ago

suyang5 commented 3 years ago

The problem shown in the picture happens when I downloaded the developer branch source code and run "../scripts/run_vtr_task.py regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain"

Possible Solution

The issue is fixed after running "python3 -m pip install -U prettytable"

jgoeders commented 2 years ago

Setup instructions will be fixed in #1914.