Open kutuusam opened 10 years ago
hey sure. What would you like to know?
-Vineeth
On Wed, Sep 24, 2014 at 9:34 AM, kutuusam notifications@github.com wrote:
I would like to know more about this Can you please contact
— Reply to this email directly or view it on GitHub https://github.com/vineethh91/ECE337-labs-and-final-project/issues/1.
Hi,
I need help for doing my ASIC design labs using Verilog.I don't know about your current position.Is it possible for you to help me if I send my work to you? .Even though I am spending most of the time on this,I am getting errors.Thank you.
I don't really have any of the tools required to run the designs themselves so I can't help debug your code for you. But if you want to send me your code chunks and describe the problem you're having I'd be glad to help you come up with solutions you may not have tried to fix the issue. On 2 Oct 2014 21:43, "kutuusam" notifications@github.com wrote:
Hi,
I need help for doing my ASIC design labs using Verilog.I don't know about your current position.Is it possible for you to help me if I send my work to you? .Even though I am spending most of the time on this,I am getting errors.Thank you.
— Reply to this email directly or view it on GitHub https://github.com/vineethh91/ECE337-labs-and-final-project/issues/1#issuecomment-57750947 .
I would like to know more about this Can you please contact