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Automatically exported from code.google.com/p/libyuv
BSD 3-Clause "New" or "Revised" License
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ios 64 bit warnings #430

Closed GoogleCodeExporter closed 9 years ago

GoogleCodeExporter commented 9 years ago 
compile for ios 64 bit.
there are casting warnings.

Original issue reported on code.google.com by fbarch...@google.com on 22 Apr 2015 at 1:05

GoogleCodeExporter commented 9 years ago 
In scale_neon64.cc

// TODO(Yang Zhang): Investigate less load instructions for
// the x/dx stepping
#define LOAD1_DATA32_LANE(vn, n)                               \
    "lsr        %5, %3, #16                    \n"             \
    "add        %6, %1, %5, lsl #2             \n"             \
    "add        %3, %3, %4                     \n"             \
    MEMACCESS(6)                                               \
    "ld1        {"#vn".s}["#n"], [%6]          \n"

%6 and %1 are 64 bit pointers, but %5 and %3 are 32 bit int's.
I think %5 (tmp) should be made into int64.
Can this line:
lsr        %5, %3, #16 

widen from %3 32 bit to %5 64 bit?

Original comment by fbarch...@google.com on 22 Apr 2015 at 1:17

GoogleCodeExporter commented 9 years ago

Original comment by fbarch...@google.com on 22 Apr 2015 at 5:30

GoogleCodeExporter commented 9 years ago 
register size warnings in ios 64 bit build

[11/18] CXX obj/source/libyuv_neon.scale_neon64.arm64.o
../../source/scale_neon64.cc:639:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(dst_width),        // %2
         ^
../../source/scale_neon64.cc:598:27: note: use constraint modifier "w"
    "ld1        {v2.4s}, [%5]                  \n"  // 0 1 2 3
                          ^~
                          %w5
../../source/scale_neon64.cc:639:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(dst_width),        // %2
         ^
../../source/scale_neon64.cc:607:5: note: use constraint modifier "w"
    LOAD2_DATA8_LANE(0)
    ^
../../source/scale_neon64.cc:584:17: note: expanded from macro 
'LOAD2_DATA8_LANE'
    "lsr        %5, %3, #16                    \n"             \
                ^
../../source/scale_neon64.cc:640:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(x),                // %3
         ^
../../source/scale_neon64.cc:607:5: note: use constraint modifier "w"
    LOAD2_DATA8_LANE(0)
    ^
../../source/scale_neon64.cc:585:17: note: expanded from macro 
'LOAD2_DATA8_LANE'
    "add        %6, %1, %5                    \n"              \
                ^
../../source/scale_neon64.cc:639:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(dst_width),        // %2
         ^
../../source/scale_neon64.cc:607:5: note: use constraint modifier "w"
    LOAD2_DATA8_LANE(0)
    ^
../../source/scale_neon64.cc:585:25: note: expanded from macro 
'LOAD2_DATA8_LANE'
    "add        %6, %1, %5                    \n"              \
                        ^
../../source/scale_neon64.cc:639:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(dst_width),        // %2
         ^
../../source/scale_neon64.cc:607:5: note: use constraint modifier "w"
    LOAD2_DATA8_LANE(0)
    ^
../../source/scale_neon64.cc:586:25: note: expanded from macro 
'LOAD2_DATA8_LANE'
    "add        %3, %3, %4                     \n"             \
                        ^
../../source/scale_neon64.cc:640:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(x),                // %3
         ^
../../source/scale_neon64.cc:607:5: note: use constraint modifier "w"
    LOAD2_DATA8_LANE(0)
    ^
../../source/scale_neon64.cc:588:38: note: expanded from macro 
'LOAD2_DATA8_LANE'
    "ld2        {v4.b, v5.b}["#n"], [%6]      \n"
                                     ^
../../source/scale_neon64.cc:639:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(dst_width),        // %2
         ^
../../source/scale_neon64.cc:608:5: note: use constraint modifier "w"
    LOAD2_DATA8_LANE(1)
    ^
../../source/scale_neon64.cc:584:17: note: expanded from macro 
'LOAD2_DATA8_LANE'
    "lsr        %5, %3, #16                    \n"             \
                ^
../../source/scale_neon64.cc:640:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(x),                // %3
         ^
../../source/scale_neon64.cc:608:5: note: use constraint modifier "w"
    LOAD2_DATA8_LANE(1)
    ^
../../source/scale_neon64.cc:585:17: note: expanded from macro 
'LOAD2_DATA8_LANE'
    "add        %6, %1, %5                    \n"              \
                ^
../../source/scale_neon64.cc:639:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(dst_width),        // %2
         ^
../../source/scale_neon64.cc:608:5: note: use constraint modifier "w"
    LOAD2_DATA8_LANE(1)
    ^
../../source/scale_neon64.cc:585:25: note: expanded from macro 
'LOAD2_DATA8_LANE'
    "add        %6, %1, %5                    \n"              \
                        ^
../../source/scale_neon64.cc:639:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(dst_width),        // %2
         ^
../../source/scale_neon64.cc:608:5: note: use constraint modifier "w"
    LOAD2_DATA8_LANE(1)
    ^
../../source/scale_neon64.cc:586:25: note: expanded from macro 
'LOAD2_DATA8_LANE'
    "add        %3, %3, %4                     \n"             \
                        ^
../../source/scale_neon64.cc:640:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(x),                // %3
         ^
../../source/scale_neon64.cc:608:5: note: use constraint modifier "w"
    LOAD2_DATA8_LANE(1)
    ^
../../source/scale_neon64.cc:588:38: note: expanded from macro 
'LOAD2_DATA8_LANE'
    "ld2        {v4.b, v5.b}["#n"], [%6]      \n"
                                     ^
../../source/scale_neon64.cc:639:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(dst_width),        // %2
         ^
../../source/scale_neon64.cc:609:5: note: use constraint modifier "w"
    LOAD2_DATA8_LANE(2)
    ^
../../source/scale_neon64.cc:584:17: note: expanded from macro 
'LOAD2_DATA8_LANE'
    "lsr        %5, %3, #16                    \n"             \
                ^
../../source/scale_neon64.cc:640:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(x),                // %3
         ^
../../source/scale_neon64.cc:609:5: note: use constraint modifier "w"
    LOAD2_DATA8_LANE(2)
    ^
../../source/scale_neon64.cc:585:17: note: expanded from macro 
'LOAD2_DATA8_LANE'
    "add        %6, %1, %5                    \n"              \
                ^
../../source/scale_neon64.cc:639:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(dst_width),        // %2
         ^
../../source/scale_neon64.cc:609:5: note: use constraint modifier "w"
    LOAD2_DATA8_LANE(2)
    ^
../../source/scale_neon64.cc:585:25: note: expanded from macro 
'LOAD2_DATA8_LANE'
    "add        %6, %1, %5                    \n"              \
                        ^
../../source/scale_neon64.cc:639:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(dst_width),        // %2
         ^
../../source/scale_neon64.cc:609:5: note: use constraint modifier "w"
    LOAD2_DATA8_LANE(2)
    ^
../../source/scale_neon64.cc:586:25: note: expanded from macro 
'LOAD2_DATA8_LANE'
    "add        %3, %3, %4                     \n"             \
                        ^
../../source/scale_neon64.cc:640:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(x),                // %3
         ^
../../source/scale_neon64.cc:609:5: note: use constraint modifier "w"
    LOAD2_DATA8_LANE(2)
    ^
../../source/scale_neon64.cc:588:38: note: expanded from macro 
'LOAD2_DATA8_LANE'
    "ld2        {v4.b, v5.b}["#n"], [%6]      \n"
                                     ^
../../source/scale_neon64.cc:639:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(dst_width),        // %2
         ^
../../source/scale_neon64.cc:610:5: note: use constraint modifier "w"
    LOAD2_DATA8_LANE(3)
    ^
../../source/scale_neon64.cc:584:17: note: expanded from macro 
'LOAD2_DATA8_LANE'
    "lsr        %5, %3, #16                    \n"             \
                ^
../../source/scale_neon64.cc:640:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(x),                // %3
         ^
../../source/scale_neon64.cc:610:5: note: use constraint modifier "w"
    LOAD2_DATA8_LANE(3)
    ^
../../source/scale_neon64.cc:585:17: note: expanded from macro 
'LOAD2_DATA8_LANE'
    "add        %6, %1, %5                    \n"              \
                ^
../../source/scale_neon64.cc:639:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(dst_width),        // %2
         ^
../../source/scale_neon64.cc:610:5: note: use constraint modifier "w"
    LOAD2_DATA8_LANE(3)
    ^
../../source/scale_neon64.cc:585:25: note: expanded from macro 
'LOAD2_DATA8_LANE'
    "add        %6, %1, %5                    \n"              \
                        ^
../../source/scale_neon64.cc:639:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(dst_width),        // %2
         ^
../../source/scale_neon64.cc:610:5: note: use constraint modifier "w"
    LOAD2_DATA8_LANE(3)
    ^
../../source/scale_neon64.cc:586:25: note: expanded from macro 
'LOAD2_DATA8_LANE'
    "add        %3, %3, %4                     \n"             \
                        ^
../../source/scale_neon64.cc:640:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(x),                // %3
         ^
../../source/scale_neon64.cc:610:5: note: use constraint modifier "w"
    LOAD2_DATA8_LANE(3)
    ^
../../source/scale_neon64.cc:588:38: note: expanded from macro 
'LOAD2_DATA8_LANE'
    "ld2        {v4.b, v5.b}["#n"], [%6]      \n"
                                     ^
../../source/scale_neon64.cc:639:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(dst_width),        // %2
         ^
../../source/scale_neon64.cc:611:5: note: use constraint modifier "w"
    LOAD2_DATA8_LANE(4)
    ^
../../source/scale_neon64.cc:584:17: note: expanded from macro 
'LOAD2_DATA8_LANE'
    "lsr        %5, %3, #16                    \n"             \
                ^
../../source/scale_neon64.cc:640:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(x),                // %3
         ^
../../source/scale_neon64.cc:611:5: note: use constraint modifier "w"
    LOAD2_DATA8_LANE(4)
    ^
../../source/scale_neon64.cc:585:17: note: expanded from macro 
'LOAD2_DATA8_LANE'
    "add        %6, %1, %5                    \n"              \
                ^
../../source/scale_neon64.cc:639:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(dst_width),        // %2
         ^
../../source/scale_neon64.cc:611:5: note: use constraint modifier "w"
    LOAD2_DATA8_LANE(4)
    ^
../../source/scale_neon64.cc:585:25: note: expanded from macro 
'LOAD2_DATA8_LANE'
    "add        %6, %1, %5                    \n"              \
                        ^
../../source/scale_neon64.cc:639:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(dst_width),        // %2
         ^
../../source/scale_neon64.cc:611:5: note: use constraint modifier "w"
    LOAD2_DATA8_LANE(4)
    ^
../../source/scale_neon64.cc:586:25: note: expanded from macro 
'LOAD2_DATA8_LANE'
    "add        %3, %3, %4                     \n"             \
                        ^
../../source/scale_neon64.cc:640:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(x),                // %3
         ^
../../source/scale_neon64.cc:611:5: note: use constraint modifier "w"
    LOAD2_DATA8_LANE(4)
    ^
../../source/scale_neon64.cc:588:38: note: expanded from macro 
'LOAD2_DATA8_LANE'
    "ld2        {v4.b, v5.b}["#n"], [%6]      \n"
                                     ^
../../source/scale_neon64.cc:639:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(dst_width),        // %2
         ^
../../source/scale_neon64.cc:612:5: note: use constraint modifier "w"
    LOAD2_DATA8_LANE(5)
    ^
../../source/scale_neon64.cc:584:17: note: expanded from macro 
'LOAD2_DATA8_LANE'
    "lsr        %5, %3, #16                    \n"             \
                ^
../../source/scale_neon64.cc:640:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(x),                // %3
         ^
../../source/scale_neon64.cc:612:5: note: use constraint modifier "w"
    LOAD2_DATA8_LANE(5)
    ^
../../source/scale_neon64.cc:585:17: note: expanded from macro 
'LOAD2_DATA8_LANE'
    "add        %6, %1, %5                    \n"              \
                ^
../../source/scale_neon64.cc:639:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(dst_width),        // %2
         ^
../../source/scale_neon64.cc:612:5: note: use constraint modifier "w"
    LOAD2_DATA8_LANE(5)
    ^
../../source/scale_neon64.cc:585:25: note: expanded from macro 
'LOAD2_DATA8_LANE'
    "add        %6, %1, %5                    \n"              \
                        ^
../../source/scale_neon64.cc:639:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(dst_width),        // %2
         ^
../../source/scale_neon64.cc:612:5: note: use constraint modifier "w"
    LOAD2_DATA8_LANE(5)
    ^
../../source/scale_neon64.cc:586:25: note: expanded from macro 
'LOAD2_DATA8_LANE'
    "add        %3, %3, %4                     \n"             \
                        ^
../../source/scale_neon64.cc:640:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(x),                // %3
         ^
../../source/scale_neon64.cc:612:5: note: use constraint modifier "w"
    LOAD2_DATA8_LANE(5)
    ^
../../source/scale_neon64.cc:588:38: note: expanded from macro 
'LOAD2_DATA8_LANE'
    "ld2        {v4.b, v5.b}["#n"], [%6]      \n"
                                     ^
../../source/scale_neon64.cc:639:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(dst_width),        // %2
         ^
../../source/scale_neon64.cc:613:5: note: use constraint modifier "w"
    LOAD2_DATA8_LANE(6)
    ^
../../source/scale_neon64.cc:584:17: note: expanded from macro 
'LOAD2_DATA8_LANE'
    "lsr        %5, %3, #16                    \n"             \
                ^
../../source/scale_neon64.cc:640:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(x),                // %3
         ^
../../source/scale_neon64.cc:613:5: note: use constraint modifier "w"
    LOAD2_DATA8_LANE(6)
    ^
../../source/scale_neon64.cc:585:17: note: expanded from macro 
'LOAD2_DATA8_LANE'
    "add        %6, %1, %5                    \n"              \
                ^
../../source/scale_neon64.cc:639:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(dst_width),        // %2
         ^
../../source/scale_neon64.cc:613:5: note: use constraint modifier "w"
    LOAD2_DATA8_LANE(6)
    ^
../../source/scale_neon64.cc:585:25: note: expanded from macro 
'LOAD2_DATA8_LANE'
    "add        %6, %1, %5                    \n"              \
                        ^
../../source/scale_neon64.cc:639:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(dst_width),        // %2
         ^
../../source/scale_neon64.cc:613:5: note: use constraint modifier "w"
    LOAD2_DATA8_LANE(6)
    ^
../../source/scale_neon64.cc:586:25: note: expanded from macro 
'LOAD2_DATA8_LANE'
    "add        %3, %3, %4                     \n"             \
                        ^
../../source/scale_neon64.cc:640:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(x),                // %3
         ^
../../source/scale_neon64.cc:613:5: note: use constraint modifier "w"
    LOAD2_DATA8_LANE(6)
    ^
../../source/scale_neon64.cc:588:38: note: expanded from macro 
'LOAD2_DATA8_LANE'
    "ld2        {v4.b, v5.b}["#n"], [%6]      \n"
                                     ^
../../source/scale_neon64.cc:639:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(dst_width),        // %2
         ^
../../source/scale_neon64.cc:614:5: note: use constraint modifier "w"
    LOAD2_DATA8_LANE(7)
    ^
../../source/scale_neon64.cc:584:17: note: expanded from macro 
'LOAD2_DATA8_LANE'
    "lsr        %5, %3, #16                    \n"             \
                ^
../../source/scale_neon64.cc:640:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(x),                // %3
         ^
../../source/scale_neon64.cc:614:5: note: use constraint modifier "w"
    LOAD2_DATA8_LANE(7)
    ^
../../source/scale_neon64.cc:585:17: note: expanded from macro 
'LOAD2_DATA8_LANE'
    "add        %6, %1, %5                    \n"              \
                ^
../../source/scale_neon64.cc:639:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(dst_width),        // %2
         ^
../../source/scale_neon64.cc:614:5: note: use constraint modifier "w"
    LOAD2_DATA8_LANE(7)
    ^
../../source/scale_neon64.cc:585:25: note: expanded from macro 
'LOAD2_DATA8_LANE'
    "add        %6, %1, %5                    \n"              \
                        ^
../../source/scale_neon64.cc:639:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(dst_width),        // %2
         ^
../../source/scale_neon64.cc:614:5: note: use constraint modifier "w"
    LOAD2_DATA8_LANE(7)
    ^
../../source/scale_neon64.cc:586:25: note: expanded from macro 
'LOAD2_DATA8_LANE'
    "add        %3, %3, %4                     \n"             \
                        ^
../../source/scale_neon64.cc:640:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(x),                // %3
         ^
../../source/scale_neon64.cc:614:5: note: use constraint modifier "w"
    LOAD2_DATA8_LANE(7)
    ^
../../source/scale_neon64.cc:588:38: note: expanded from macro 
'LOAD2_DATA8_LANE'
    "ld2        {v4.b, v5.b}["#n"], [%6]      \n"
                                     ^
../../source/scale_neon64.cc:946:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(dst_width),        // %2
         ^
../../source/scale_neon64.cc:931:5: note: use constraint modifier "w"
    LOAD1_DATA32_LANE(v0, 0)
    ^

Original comment by phthor...@gmail.com on 22 Apr 2015 at 7:14

GoogleCodeExporter commented 9 years ago 
../../source/scale_neon64.cc:919:17: note: expanded from macro 
'LOAD1_DATA32_LANE'
    "lsr        %5, %3, #16                    \n"             \
                ^
../../source/scale_neon64.cc:947:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(x),                // %3
         ^
../../source/scale_neon64.cc:931:5: note: use constraint modifier "w"
    LOAD1_DATA32_LANE(v0, 0)
    ^
../../source/scale_neon64.cc:920:17: note: expanded from macro 
'LOAD1_DATA32_LANE'
    "add        %6, %1, %5, lsl #2             \n"             \
                ^
../../source/scale_neon64.cc:946:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(dst_width),        // %2
         ^
../../source/scale_neon64.cc:931:5: note: use constraint modifier "w"
    LOAD1_DATA32_LANE(v0, 0)
    ^
../../source/scale_neon64.cc:920:25: note: expanded from macro 
'LOAD1_DATA32_LANE'
    "add        %6, %1, %5, lsl #2             \n"             \
                        ^
../../source/scale_neon64.cc:946:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(dst_width),        // %2
         ^
../../source/scale_neon64.cc:931:5: note: use constraint modifier "w"
    LOAD1_DATA32_LANE(v0, 0)
    ^
../../source/scale_neon64.cc:921:25: note: expanded from macro 
'LOAD1_DATA32_LANE'
    "add        %3, %3, %4                     \n"             \
                        ^
../../source/scale_neon64.cc:947:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(x),                // %3
         ^
../../source/scale_neon64.cc:931:5: note: use constraint modifier "w"
    LOAD1_DATA32_LANE(v0, 0)
    ^
../../source/scale_neon64.cc:923:35: note: expanded from macro 
'LOAD1_DATA32_LANE'
    "ld1        {"#vn".s}["#n"], [%6]          \n"
                                  ^
../../source/scale_neon64.cc:946:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(dst_width),        // %2
         ^
../../source/scale_neon64.cc:932:5: note: use constraint modifier "w"
    LOAD1_DATA32_LANE(v0, 1)
    ^
../../source/scale_neon64.cc:919:17: note: expanded from macro 
'LOAD1_DATA32_LANE'
    "lsr        %5, %3, #16                    \n"             \
                ^
../../source/scale_neon64.cc:947:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(x),                // %3
         ^
../../source/scale_neon64.cc:932:5: note: use constraint modifier "w"
    LOAD1_DATA32_LANE(v0, 1)
    ^
../../source/scale_neon64.cc:920:17: note: expanded from macro 
'LOAD1_DATA32_LANE'
    "add        %6, %1, %5, lsl #2             \n"             \
                ^
../../source/scale_neon64.cc:946:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(dst_width),        // %2
         ^
../../source/scale_neon64.cc:932:5: note: use constraint modifier "w"
    LOAD1_DATA32_LANE(v0, 1)
    ^
../../source/scale_neon64.cc:920:25: note: expanded from macro 
'LOAD1_DATA32_LANE'
    "add        %6, %1, %5, lsl #2             \n"             \
                        ^
../../source/scale_neon64.cc:946:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(dst_width),        // %2
         ^
../../source/scale_neon64.cc:932:5: note: use constraint modifier "w"
    LOAD1_DATA32_LANE(v0, 1)
    ^
../../source/scale_neon64.cc:921:25: note: expanded from macro 
'LOAD1_DATA32_LANE'
    "add        %3, %3, %4                     \n"             \
                        ^
../../source/scale_neon64.cc:947:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(x),                // %3
         ^
../../source/scale_neon64.cc:932:5: note: use constraint modifier "w"
    LOAD1_DATA32_LANE(v0, 1)
    ^
../../source/scale_neon64.cc:923:35: note: expanded from macro 
'LOAD1_DATA32_LANE'
    "ld1        {"#vn".s}["#n"], [%6]          \n"
                                  ^
../../source/scale_neon64.cc:946:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(dst_width),        // %2
         ^
../../source/scale_neon64.cc:933:5: note: use constraint modifier "w"
    LOAD1_DATA32_LANE(v0, 2)
    ^
../../source/scale_neon64.cc:919:17: note: expanded from macro 
'LOAD1_DATA32_LANE'
    "lsr        %5, %3, #16                    \n"             \
                ^
../../source/scale_neon64.cc:947:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(x),                // %3
         ^
../../source/scale_neon64.cc:933:5: note: use constraint modifier "w"
    LOAD1_DATA32_LANE(v0, 2)
    ^
../../source/scale_neon64.cc:920:17: note: expanded from macro 
'LOAD1_DATA32_LANE'
    "add        %6, %1, %5, lsl #2             \n"             \
                ^
../../source/scale_neon64.cc:946:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(dst_width),        // %2
         ^
../../source/scale_neon64.cc:933:5: note: use constraint modifier "w"
    LOAD1_DATA32_LANE(v0, 2)
    ^
../../source/scale_neon64.cc:920:25: note: expanded from macro 
'LOAD1_DATA32_LANE'
    "add        %6, %1, %5, lsl #2             \n"             \
                        ^
../../source/scale_neon64.cc:946:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(dst_width),        // %2
         ^
../../source/scale_neon64.cc:933:5: note: use constraint modifier "w"
    LOAD1_DATA32_LANE(v0, 2)
    ^
../../source/scale_neon64.cc:921:25: note: expanded from macro 
'LOAD1_DATA32_LANE'
    "add        %3, %3, %4                     \n"             \
                        ^
../../source/scale_neon64.cc:947:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(x),                // %3
         ^
../../source/scale_neon64.cc:933:5: note: use constraint modifier "w"
    LOAD1_DATA32_LANE(v0, 2)
    ^
../../source/scale_neon64.cc:923:35: note: expanded from macro 
'LOAD1_DATA32_LANE'
    "ld1        {"#vn".s}["#n"], [%6]          \n"
                                  ^
../../source/scale_neon64.cc:946:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(dst_width),        // %2
         ^
../../source/scale_neon64.cc:934:5: note: use constraint modifier "w"
    LOAD1_DATA32_LANE(v0, 3)
    ^
../../source/scale_neon64.cc:919:17: note: expanded from macro 
'LOAD1_DATA32_LANE'
    "lsr        %5, %3, #16                    \n"             \
                ^
../../source/scale_neon64.cc:947:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(x),                // %3
         ^
../../source/scale_neon64.cc:934:5: note: use constraint modifier "w"
    LOAD1_DATA32_LANE(v0, 3)
    ^
../../source/scale_neon64.cc:920:17: note: expanded from macro 
'LOAD1_DATA32_LANE'
    "add        %6, %1, %5, lsl #2             \n"             \
                ^
../../source/scale_neon64.cc:946:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(dst_width),        // %2
         ^
../../source/scale_neon64.cc:934:5: note: use constraint modifier "w"
    LOAD1_DATA32_LANE(v0, 3)
    ^
../../source/scale_neon64.cc:920:25: note: expanded from macro 
'LOAD1_DATA32_LANE'
    "add        %6, %1, %5, lsl #2             \n"             \
                        ^
../../source/scale_neon64.cc:946:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(dst_width),        // %2
         ^
../../source/scale_neon64.cc:934:5: note: use constraint modifier "w"
    LOAD1_DATA32_LANE(v0, 3)
    ^
../../source/scale_neon64.cc:921:25: note: expanded from macro 
'LOAD1_DATA32_LANE'
    "add        %3, %3, %4                     \n"             \
                        ^
../../source/scale_neon64.cc:947:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(x),                // %3
         ^
../../source/scale_neon64.cc:934:5: note: use constraint modifier "w"
    LOAD1_DATA32_LANE(v0, 3)
    ^
../../source/scale_neon64.cc:923:35: note: expanded from macro 
'LOAD1_DATA32_LANE'
    "ld1        {"#vn".s}["#n"], [%6]          \n"
                                  ^
../../source/scale_neon64.cc:946:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(dst_width),        // %2
         ^
../../source/scale_neon64.cc:935:5: note: use constraint modifier "w"
    LOAD1_DATA32_LANE(v1, 0)
    ^
../../source/scale_neon64.cc:919:17: note: expanded from macro 
'LOAD1_DATA32_LANE'
    "lsr        %5, %3, #16                    \n"             \
                ^
../../source/scale_neon64.cc:947:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(x),                // %3
         ^
../../source/scale_neon64.cc:935:5: note: use constraint modifier "w"
    LOAD1_DATA32_LANE(v1, 0)
    ^
../../source/scale_neon64.cc:920:17: note: expanded from macro 
'LOAD1_DATA32_LANE'
    "add        %6, %1, %5, lsl #2             \n"             \
                ^
../../source/scale_neon64.cc:946:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(dst_width),        // %2
         ^
../../source/scale_neon64.cc:935:5: note: use constraint modifier "w"
    LOAD1_DATA32_LANE(v1, 0)
    ^
../../source/scale_neon64.cc:920:25: note: expanded from macro 
'LOAD1_DATA32_LANE'
    "add        %6, %1, %5, lsl #2             \n"             \
                        ^
../../source/scale_neon64.cc:946:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(dst_width),        // %2
         ^
../../source/scale_neon64.cc:935:5: note: use constraint modifier "w"
    LOAD1_DATA32_LANE(v1, 0)
    ^
../../source/scale_neon64.cc:921:25: note: expanded from macro 
'LOAD1_DATA32_LANE'
    "add        %3, %3, %4                     \n"             \
                        ^
../../source/scale_neon64.cc:947:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(x),                // %3
         ^
../../source/scale_neon64.cc:935:5: note: use constraint modifier "w"
    LOAD1_DATA32_LANE(v1, 0)
    ^
../../source/scale_neon64.cc:923:35: note: expanded from macro 
'LOAD1_DATA32_LANE'
    "ld1        {"#vn".s}["#n"], [%6]          \n"
                                  ^
../../source/scale_neon64.cc:946:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(dst_width),        // %2
         ^
../../source/scale_neon64.cc:936:5: note: use constraint modifier "w"
    LOAD1_DATA32_LANE(v1, 1)
    ^
../../source/scale_neon64.cc:919:17: note: expanded from macro 
'LOAD1_DATA32_LANE'
    "lsr        %5, %3, #16                    \n"             \
                ^
../../source/scale_neon64.cc:947:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(x),                // %3
         ^
../../source/scale_neon64.cc:936:5: note: use constraint modifier "w"
    LOAD1_DATA32_LANE(v1, 1)
    ^
../../source/scale_neon64.cc:920:17: note: expanded from macro 
'LOAD1_DATA32_LANE'
    "add        %6, %1, %5, lsl #2             \n"             \
                ^
../../source/scale_neon64.cc:946:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(dst_width),        // %2
         ^
../../source/scale_neon64.cc:936:5: note: use constraint modifier "w"
    LOAD1_DATA32_LANE(v1, 1)
    ^
../../source/scale_neon64.cc:920:25: note: expanded from macro 
'LOAD1_DATA32_LANE'
    "add        %6, %1, %5, lsl #2             \n"             \
                        ^
../../source/scale_neon64.cc:946:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(dst_width),        // %2
         ^
../../source/scale_neon64.cc:936:5: note: use constraint modifier "w"
    LOAD1_DATA32_LANE(v1, 1)
    ^
../../source/scale_neon64.cc:921:25: note: expanded from macro 
'LOAD1_DATA32_LANE'
    "add        %3, %3, %4                     \n"             \
                        ^
../../source/scale_neon64.cc:947:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(x),                // %3
         ^
../../source/scale_neon64.cc:936:5: note: use constraint modifier "w"
    LOAD1_DATA32_LANE(v1, 1)
    ^
../../source/scale_neon64.cc:923:35: note: expanded from macro 
'LOAD1_DATA32_LANE'
    "ld1        {"#vn".s}["#n"], [%6]          \n"
                                  ^
../../source/scale_neon64.cc:946:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(dst_width),        // %2
         ^
../../source/scale_neon64.cc:937:5: note: use constraint modifier "w"
    LOAD1_DATA32_LANE(v1, 2)
    ^
../../source/scale_neon64.cc:919:17: note: expanded from macro 
'LOAD1_DATA32_LANE'
    "lsr        %5, %3, #16                    \n"             \
                ^
../../source/scale_neon64.cc:947:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(x),                // %3
         ^
../../source/scale_neon64.cc:937:5: note: use constraint modifier "w"
    LOAD1_DATA32_LANE(v1, 2)
    ^
../../source/scale_neon64.cc:920:17: note: expanded from macro 
'LOAD1_DATA32_LANE'
    "add        %6, %1, %5, lsl #2             \n"             \
                ^
../../source/scale_neon64.cc:946:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(dst_width),        // %2
         ^
../../source/scale_neon64.cc:937:5: note: use constraint modifier "w"
    LOAD1_DATA32_LANE(v1, 2)
    ^
../../source/scale_neon64.cc:920:25: note: expanded from macro 
'LOAD1_DATA32_LANE'
    "add        %6, %1, %5, lsl #2             \n"             \
                        ^
../../source/scale_neon64.cc:946:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(dst_width),        // %2
         ^
../../source/scale_neon64.cc:937:5: note: use constraint modifier "w"
    LOAD1_DATA32_LANE(v1, 2)
    ^
../../source/scale_neon64.cc:921:25: note: expanded from macro 
'LOAD1_DATA32_LANE'
    "add        %3, %3, %4                     \n"             \
                        ^
../../source/scale_neon64.cc:947:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(x),                // %3
         ^
../../source/scale_neon64.cc:937:5: note: use constraint modifier "w"
    LOAD1_DATA32_LANE(v1, 2)
    ^
../../source/scale_neon64.cc:923:35: note: expanded from macro 
'LOAD1_DATA32_LANE'
    "ld1        {"#vn".s}["#n"], [%6]          \n"
                                  ^
../../source/scale_neon64.cc:946:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(dst_width),        // %2
         ^
../../source/scale_neon64.cc:938:5: note: use constraint modifier "w"
    LOAD1_DATA32_LANE(v1, 3)
    ^
../../source/scale_neon64.cc:919:17: note: expanded from macro 
'LOAD1_DATA32_LANE'
    "lsr        %5, %3, #16                    \n"             \
                ^
../../source/scale_neon64.cc:947:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(x),                // %3
         ^
../../source/scale_neon64.cc:938:5: note: use constraint modifier "w"
    LOAD1_DATA32_LANE(v1, 3)
    ^
../../source/scale_neon64.cc:920:17: note: expanded from macro 
'LOAD1_DATA32_LANE'
    "add        %6, %1, %5, lsl #2             \n"             \
                ^
../../source/scale_neon64.cc:946:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(dst_width),        // %2
         ^
../../source/scale_neon64.cc:938:5: note: use constraint modifier "w"
    LOAD1_DATA32_LANE(v1, 3)
    ^
../../source/scale_neon64.cc:920:25: note: expanded from macro 
'LOAD1_DATA32_LANE'
    "add        %6, %1, %5, lsl #2             \n"             \
                        ^
../../source/scale_neon64.cc:946:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(dst_width),        // %2
         ^
../../source/scale_neon64.cc:938:5: note: use constraint modifier "w"
    LOAD1_DATA32_LANE(v1, 3)
    ^
../../source/scale_neon64.cc:921:25: note: expanded from macro 
'LOAD1_DATA32_LANE'
    "add        %3, %3, %4                     \n"             \
                        ^
../../source/scale_neon64.cc:947:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(x),                // %3
         ^
../../source/scale_neon64.cc:938:5: note: use constraint modifier "w"
    LOAD1_DATA32_LANE(v1, 3)
    ^
../../source/scale_neon64.cc:923:35: note: expanded from macro 
'LOAD1_DATA32_LANE'
    "ld1        {"#vn".s}["#n"], [%6]          \n"
                                  ^
../../source/scale_neon64.cc:1015:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(dst_width),        // %2
         ^
../../source/scale_neon64.cc:975:27: note: use constraint modifier "w"
    "ld1        {v2.4s}, [%5]                  \n"  // 0 1 2 3
                          ^~
                          %w5
../../source/scale_neon64.cc:1015:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(dst_width),        // %2
         ^
../../source/scale_neon64.cc:985:5: note: use constraint modifier "w"
    LOAD2_DATA32_LANE(v0, v1, 0)
    ^
../../source/scale_neon64.cc:961:17: note: expanded from macro 
'LOAD2_DATA32_LANE'
    "lsr        %5, %3, #16                           \n"      \
                ^
../../source/scale_neon64.cc:1016:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(x),                // %3
         ^
../../source/scale_neon64.cc:985:5: note: use constraint modifier "w"
    LOAD2_DATA32_LANE(v0, v1, 0)
    ^
../../source/scale_neon64.cc:962:17: note: expanded from macro 
'LOAD2_DATA32_LANE'
    "add        %6, %1, %5, lsl #2                    \n"      \
                ^
../../source/scale_neon64.cc:1015:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(dst_width),        // %2
         ^
../../source/scale_neon64.cc:985:5: note: use constraint modifier "w"
    LOAD2_DATA32_LANE(v0, v1, 0)
    ^
../../source/scale_neon64.cc:962:25: note: expanded from macro 
'LOAD2_DATA32_LANE'
    "add        %6, %1, %5, lsl #2                    \n"      \
                        ^
../../source/scale_neon64.cc:1015:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(dst_width),        // %2
         ^
../../source/scale_neon64.cc:985:5: note: use constraint modifier "w"
    LOAD2_DATA32_LANE(v0, v1, 0)
    ^
../../source/scale_neon64.cc:963:25: note: expanded from macro 
'LOAD2_DATA32_LANE'
    "add        %3, %3, %4                            \n"      \
                        ^
../../source/scale_neon64.cc:1016:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(x),                // %3
         ^
../../source/scale_neon64.cc:985:5: note: use constraint modifier "w"
    LOAD2_DATA32_LANE(v0, v1, 0)
    ^
../../source/scale_neon64.cc:965:46: note: expanded from macro 
'LOAD2_DATA32_LANE'
    "ld2        {"#vn1".s, "#vn2".s}["#n"], [%6]      \n"
                                             ^
../../source/scale_neon64.cc:1015:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(dst_width),        // %2
         ^
../../source/scale_neon64.cc:986:5: note: use constraint modifier "w"
    LOAD2_DATA32_LANE(v0, v1, 1)
    ^
../../source/scale_neon64.cc:961:17: note: expanded from macro 
'LOAD2_DATA32_LANE'
    "lsr        %5, %3, #16                           \n"      \
                ^
../../source/scale_neon64.cc:1016:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(x),                // %3
         ^
../../source/scale_neon64.cc:986:5: note: use constraint modifier "w"
    LOAD2_DATA32_LANE(v0, v1, 1)
    ^
../../source/scale_neon64.cc:962:17: note: expanded from macro 
'LOAD2_DATA32_LANE'
    "add        %6, %1, %5, lsl #2                    \n"      \
                ^
../../source/scale_neon64.cc:1015:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(dst_width),        // %2
         ^
../../source/scale_neon64.cc:986:5: note: use constraint modifier "w"
    LOAD2_DATA32_LANE(v0, v1, 1)
    ^
../../source/scale_neon64.cc:962:25: note: expanded from macro 
'LOAD2_DATA32_LANE'
    "add        %6, %1, %5, lsl #2                    \n"      \
                        ^
../../source/scale_neon64.cc:1015:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(dst_width),        // %2
         ^
../../source/scale_neon64.cc:986:5: note: use constraint modifier "w"
    LOAD2_DATA32_LANE(v0, v1, 1)
    ^
../../source/scale_neon64.cc:963:25: note: expanded from macro 
'LOAD2_DATA32_LANE'
    "add        %3, %3, %4                            \n"      \
                        ^
../../source/scale_neon64.cc:1016:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(x),                // %3
         ^
../../source/scale_neon64.cc:986:5: note: use constraint modifier "w"
    LOAD2_DATA32_LANE(v0, v1, 1)
    ^
../../source/scale_neon64.cc:965:46: note: expanded from macro 
'LOAD2_DATA32_LANE'
    "ld2        {"#vn1".s, "#vn2".s}["#n"], [%6]      \n"
                                             ^
../../source/scale_neon64.cc:1015:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(dst_width),        // %2
         ^
../../source/scale_neon64.cc:987:5: note: use constraint modifier "w"
    LOAD2_DATA32_LANE(v0, v1, 2)
    ^
../../source/scale_neon64.cc:961:17: note: expanded from macro 
'LOAD2_DATA32_LANE'
    "lsr        %5, %3, #16                           \n"      \
                ^
../../source/scale_neon64.cc:1016:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(x),                // %3
         ^
../../source/scale_neon64.cc:987:5: note: use constraint modifier "w"
    LOAD2_DATA32_LANE(v0, v1, 2)
    ^
../../source/scale_neon64.cc:962:17: note: expanded from macro 
'LOAD2_DATA32_LANE'
    "add        %6, %1, %5, lsl #2                    \n"      \
                ^
../../source/scale_neon64.cc:1015:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(dst_width),        // %2
         ^
../../source/scale_neon64.cc:987:5: note: use constraint modifier "w"
    LOAD2_DATA32_LANE(v0, v1, 2)
    ^
../../source/scale_neon64.cc:962:25: note: expanded from macro 
'LOAD2_DATA32_LANE'
    "add        %6, %1, %5, lsl #2                    \n"      \
                        ^
../../source/scale_neon64.cc:1015:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(dst_width),        // %2
         ^
../../source/scale_neon64.cc:987:5: note: use constraint modifier "w"
    LOAD2_DATA32_LANE(v0, v1, 2)
    ^
../../source/scale_neon64.cc:963:25: note: expanded from macro 
'LOAD2_DATA32_LANE'
    "add        %3, %3, %4                            \n"      \
                        ^
../../source/scale_neon64.cc:1016:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(x),                // %3
         ^
../../source/scale_neon64.cc:987:5: note: use constraint modifier "w"
    LOAD2_DATA32_LANE(v0, v1, 2)
    ^
../../source/scale_neon64.cc:965:46: note: expanded from macro 
'LOAD2_DATA32_LANE'
    "ld2        {"#vn1".s, "#vn2".s}["#n"], [%6]      \n"
                                             ^
../../source/scale_neon64.cc:1015:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(dst_width),        // %2
         ^
../../source/scale_neon64.cc:988:5: note: use constraint modifier "w"
    LOAD2_DATA32_LANE(v0, v1, 3)
    ^
../../source/scale_neon64.cc:961:17: note: expanded from macro 
'LOAD2_DATA32_LANE'
    "lsr        %5, %3, #16                           \n"      \
                ^
../../source/scale_neon64.cc:1016:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(x),                // %3
         ^
../../source/scale_neon64.cc:988:5: note: use constraint modifier "w"
    LOAD2_DATA32_LANE(v0, v1, 3)
    ^
../../source/scale_neon64.cc:962:17: note: expanded from macro 
'LOAD2_DATA32_LANE'
    "add        %6, %1, %5, lsl #2                    \n"      \
                ^
../../source/scale_neon64.cc:1015:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(dst_width),        // %2
         ^
../../source/scale_neon64.cc:988:5: note: use constraint modifier "w"
    LOAD2_DATA32_LANE(v0, v1, 3)
    ^
../../source/scale_neon64.cc:962:25: note: expanded from macro 
'LOAD2_DATA32_LANE'
    "add        %6, %1, %5, lsl #2                    \n"      \
                        ^
../../source/scale_neon64.cc:1015:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(dst_width),        // %2
         ^
../../source/scale_neon64.cc:988:5: note: use constraint modifier "w"
    LOAD2_DATA32_LANE(v0, v1, 3)
    ^
../../source/scale_neon64.cc:963:25: note: expanded from macro 
'LOAD2_DATA32_LANE'
    "add        %3, %3, %4                            \n"      \
                        ^
../../source/scale_neon64.cc:1016:10: warning: value size does not match 
register size specified by the constraint and modifier [-Wasm-operand-widths]
    "+r"(x),                // %3
         ^
../../source/scale_neon64.cc:988:5: note: use constraint modifier "w"
    LOAD2_DATA32_LANE(v0, v1, 3)
    ^
../../source/scale_neon64.cc:965:46: note: expanded from macro 
'LOAD2_DATA32_LANE'
    "ld2        {"#vn1".s, "#vn2".s}["#n"], [%6]      \n"
                                             ^
102 warnings generated.

Original comment by phthor...@gmail.com on 22 Apr 2015 at 7:15

GoogleCodeExporter commented 9 years ago 
disassembly shows 64 bit registers (eg x0) are used for int.  e.g. most 
functions use int width for loop counter.
otool -tV ./out_ios/Release-iphoneos/obj/source/libyuv_neon.scale_neon64.arm64.o

_ScaleRowDown2_NEON:
0000000000000000        ld2.16b { v0, v1 }, [x0], #32
0000000000000004        subs    x3, x3, #16
0000000000000008        st1.16b { v1 }, [x2], #16
000000000000000c        b.gt    _ScaleRowDown2_NEON
0000000000000010        ret

Original comment by phthor...@gmail.com on 22 Apr 2015 at 8:59

GoogleCodeExporter commented 9 years ago 
To avoid the casting warnings for ios 64bit, I think we can widen %2, %3, %4 
from 32 bit to 64 bit. I will try to fix it.

Original comment by yang.zh...@arm.com on 23 Apr 2015 at 6:22

GoogleCodeExporter commented 9 years ago 
[34/301] CXX obj/source/libyuv_neon.row_neon64.arm64.o
../../source/row_neon64.cc:1400:9: warning: value size does not match register 
size specified by the constraint and modifier [-Wasm-operand-widths]
    "r"(dither4),    // %2
        ^
../../source/row_neon64.cc:1390:17: note: use constraint modifier "w"
    "subs       %3, %3, #8                     \n"  // 8 processed per loop.
                ^~
                %w3
../../source/row_neon64.cc:1400:9: warning: value size does not match register 
size specified by the constraint and modifier [-Wasm-operand-widths]
    "r"(dither4),    // %2
        ^
../../source/row_neon64.cc:1390:21: note: use constraint modifier "w"
    "subs       %3, %3, #8                     \n"  // 8 processed per loop.
                    ^~
                    %w3
2 warnings generated.

Original comment by fbarch...@google.com on 27 Apr 2015 at 11:18

GoogleCodeExporter commented 9 years ago 
fixed in r1382

Original comment by fbarch...@google.com on 28 Apr 2015 at 12:07