Phase II Lab/Experiment Hosting/ Rehosting Request for Very Large Scale Integration Lab (VLSI) IIITH

[mrudhvika940]

Hosting details :

• Hosting Unit(Lab) Name : Very Large Scale Integration Lab (VLSI)
• Repository URL : https://github.com/virtual-labs/vlsi-iiith
• Branch/Tag : master/v1.1.3
• Contact Person : Mrudhvika

[mrudhvika940]

Hosting details :

• Hosting Unit(Lab) Name : Very Large Scale Integration Lab (VLSI)
• Repository URL : https://github.com/virtual-labs/vlsi-iiith
• Branch/Tag : master/v1.1.4
• Contact Person : Mrudhvika

[sravanthimodepu]

@mrudhvika940

Hosted URL of Lab: http://cse14-iiith.vlabs.ac.in/ Branch: Master Tag: v1.1.4

[sravanthimodepu]

Request to re-host:

• Hosting Unit(Lab) Name : Very Large Scale Integration Lab (VLSI)
• Repository URL : https://github.com/virtual-labs/vlsi-iiith
• Branch/Tag : master/v1.1.5
• Contact Person : Mrudhvika

[pavanchow]

@sravanthimodepu

Hosted Very Large Scale Integration Lab (VLSI) URL of Lab: http://cse14-iiith.vlabs.ac.in/ Branch: Master Tag: v1.1.5

Please check and approve. NOTE: IF NOT APPROVED WITHIN 3 DAYS, SOURCES WILL BE AUTOMATICALLY REVERTED TO OLDER VERSION.

[sravanthimodepu]

Repo Owner Details Name - Sravanthi GitHub handle - sravanthimodepu Email id - sravanthimodepu@vlabs.ac.in

Lab Name: VLSI Lab

List of Experiments and Repositories: | No.| Experiment Name | Experiment repository URL | Branch | Tag

1. Schematic Design Of Transistor Level Inverter - https://github.com/virtual-labs/exp-transistor-level-inverter-iiith - main - v1.0.0
2. Schematic Design Of Transistor Level NAND & NOR Gate - https://github.com/virtual-labs/exp-transistor-level-nand-iiith - main - v1.0.0
3. Schematic Design Of Transistor Level XOR & XNOR Gate - https://github.com/virtual-labs/exp-transistor-level-xor-iiith - main - v1.0.0
4. Schematic Design Of Pass Transistor Logic & Multiplexer - https://github.com/virtual-labs/exp-pass-transistor-logic-iiith - main- v1.0.0
5. Delay Estimation In Chain Of Inverters - https://github.com/virtual-labs/exp-chain-of-inverters-iiith - main - v1.0.0
6. Schematic Design Of D-Latch and D-Flip Flop - https://github.com/virtual-labs/exp-d-latch-and-d-flip-flop-iiith - main - v1.0.0
7. Spice Code Platform - https://github.com/virtual-labs/exp-spice-code-platform-iiith - main - v1.0.0
8. Design Of D-Flip Flop Using Verilog - https://github.com/virtual-labs/exp-d-flip-flop-verilog-iiith - main - v1.0.0
9. Design Of Digital Circuits Using Verilog - https://github.com/virtual-labs/exp-digital-circuits-verilog-iiith - main - v1.0.0
10. Layout Design - https://github.com/virtual-labs/exp-layout-design-iiith - main - v1.0.0

Lab url: http://cse14-iiith.vlabs.ac.in/

Introduction: A single chip sized of few millimeters may have Millions of transistors in it for example a microprocessor is a VLSI device. Very Large Scale Integration (VLSI) is the process of creating integrated circuits by combining large numbers of transistors into a single chip.

This lab provides good understanding and learning opportunity of VLSI designing for users. There are ten experiments in this lab, which covers following aspects of VLSI designing.

• First six experiments provide GUI interface of schematic design and simulation results of various circuits.
• Seventh experiment provides WEB based Spice code simulation platform. User can learn circuit design using Spice coding.
• Eighth and ninth experiments provide digital circuit designing using Verilog code for which a web based Verilog simulation platform is provided. User can test any level of Verilog code in ninth experiment.
• Tenth experiment provides GUI interface of physical (layout) design of various circuits. By this experiment user can learn design rules (DRCs) for layout design and can test design rules of their designs.

Objective: This lab provides good understanding and learning opportunity of VLSI designing for users

Course Alignment: The present lab is aligned with VLSI course structure. The experiments touch on most topics covered in such courses in most curricula.

Target Audience: For the students of UG-ECE and PG-ECE.

[sravanthimodepu]

Repo Owner Details Name - Sravanthi GitHub handle - sravanthimodepu Email id - sravanthimodepu@vlabs.ac.in

Lab Name: VLSI Lab

List of Experiments and Repositories: | No.| Experiment Name | Experiment repository URL | Branch | Tag

1. Schematic Design Of Transistor Level Inverter - https://github.com/virtual-labs/exp-transistor-level-inverter-iiith - main - v1.0.1
2. Schematic Design Of Transistor Level NAND & NOR Gate - https://github.com/virtual-labs/exp-transistor-level-nand-iiith - main - v1.0.1
3. Schematic Design Of Transistor Level XOR & XNOR Gate - https://github.com/virtual-labs/exp-transistor-level-xor-iiith - main - v1.0.1
4. Schematic Design Of Pass Transistor Logic & Multiplexer - https://github.com/virtual-labs/exp-pass-transistor-logic-iiith - main- v1.0.1
5. Delay Estimation In Chain Of Inverters - https://github.com/virtual-labs/exp-chain-of-inverters-iiith - main - v1.0.1
6. Schematic Design Of D-Latch and D-Flip Flop - https://github.com/virtual-labs/exp-d-latch-and-d-flip-flop-iiith - main - v1.0.1
7. Spice Code Platform - https://github.com/virtual-labs/exp-spice-code-platform-iiith - main - v1.0.1
8. Design Of D-Flip Flop Using Verilog - https://github.com/virtual-labs/exp-d-flip-flop-verilog-iiith - main - v1.0.1
9. Design Of Digital Circuits Using Verilog - https://github.com/virtual-labs/exp-digital-circuits-verilog-iiith - main - v1.0.1
10. Layout Design - https://github.com/virtual-labs/exp-layout-design-iiith - main - v1.0.1

Lab url: http://cse14-iiith.vlabs.ac.in/

Introduction: A single chip sized of few millimeters may have Millions of transistors in it for example a microprocessor is a VLSI device. Very Large Scale Integration (VLSI) is the process of creating integrated circuits by combining large numbers of transistors into a single chip.

This lab provides good understanding and learning opportunity of VLSI designing for users. There are ten experiments in this lab, which covers following aspects of VLSI designing.

• First six experiments provide GUI interface of schematic design and simulation results of various circuits.
• Seventh experiment provides WEB based Spice code simulation platform. User can learn circuit design using Spice coding.
• Eighth and ninth experiments provide digital circuit designing using Verilog code for which a web based Verilog simulation platform is provided. User can test any level of Verilog code in ninth experiment.
• Tenth experiment provides GUI interface of physical (layout) design of various circuits. By this experiment user can learn design rules (DRCs) for layout design and can test design rules of their designs.

Please note:

• This lab requires few Software Dependencies to run the Simulations

  1. Adobe Flash Plugin, Java1.7, Java3D 1.5.2 (The Java 3D API enables the creation of three-dimensional graphics applications and Internet-based 3D applets)
  2. Browsers Firefox 50 and its below versions, internet explorer.
  3. IcedTea Plugin for Linux Operating System.

• We recommend the following for the smooth running of these simulations

  1. Install Adobe Flash Plugin - This will enable you to run the experiments that need Flash support. Please follow the link to install the Flash Plugin
  2. Install VirtualBox - Virtual Labs offers a free download of a customized VirtualBox with the required pre-installed software dependencies(Java 1.7, Java3D-1.5.2, IcedTea Plugin, and Adobe Flash Plugin). Please follow the link to download, install and use VirtualBox for Virtual Labs.

Objective: This lab provides good understanding and learning opportunity of VLSI designing for users

Course Alignment: The present lab is aligned with VLSI course structure. The experiments touch on most topics covered in such courses in most curricula.

Target Audience: For the students of UG-ECE and PG-ECE.

[pavanchow]

@sravanthimodepu

Hosted Very Large Scale Integration Lab (VLSI) URL of Lab: http://cse14-iiith.vlabs.ac.in/ Branch: Master

Please check and approve.

[sravanthimodepu]

@pavanchow

Please update the Introduction with prerequisites related content which is mentioned in the above issue.

[pavanchow]

@sravanthimodepu

Hosted Very Large Scale Integration Lab (VLSI) URL of Lab: http://cse14-iiith.vlabs.ac.in/ Branch: Master

Please check and approve.

[ravikiran2020]

Rehosting the lab with Bug Report and Rating Feature