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vproc
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vicuna
RISC-V Zve32x Vector Coprocessor
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How to handle "30525: Illegal instruction (hart 0) at PC 0x0000208c: 0x304022f3"?
#123
deeplearner92
opened
2 months ago
0
How to Handle conv + bias in conv_3x3 for input(int8) * weight(int8) + bias(int32)?
#122
Haleski47
opened
4 months ago
0
Applications hang indefinitely on Verilator when size of data cache is different than 0
#121
maheshejs
opened
11 months ago
1
remove double slashes
#120
lianakoleva
opened
12 months ago
0
Certain applications when executed with dual and triple pipeline configurations on verilated model of Vicuna hang indefinittely
#119
AnjaliVerma1314
opened
1 year ago
0
Machine mode CSRs not accessible with Ibex host core when using Vicuna's verilated model
#118
AnjaliVerma1314
opened
1 year ago
1
Ci progs
#117
PhilippvK
closed
1 year ago
1
Fix CI
#116
PhilippvK
opened
1 year ago
0
Reserved word not implemented: 'config'
#115
latifbhatti
closed
1 year ago
1
Error in Questasim Simulation
#114
aaqdas
opened
1 year ago
0
Added runtime.o
#113
aaqdas
opened
1 year ago
0
'Illegal Instruction' when executing sign and zero extend functions when destination LMUL=8
#112
ParkerJones567
opened
1 year ago
0
Combinatorial Loop Alert while Generating bitstream for vicuna using CV32E40X as a scalar core
#111
Nikhil-311293
opened
1 year ago
4
Floating point support.
#110
Nikhil-311293
opened
1 year ago
0
Divide
#109
s-hfarooq
opened
2 years ago
0
498 integrate
#108
timot3
closed
2 years ago
0
Fix for #100
#107
moimfeld
closed
2 years ago
4
fail to set VREG_W=2048
#106
schwa1z
closed
2 years ago
2
No way to clear a cache error?
#105
stevobailey
opened
2 years ago
0
Vicuna + Ibex and WFI
#104
stevobailey
opened
2 years ago
0
narrowing instructions are never popped from the instruction queue
#103
moimfeld
opened
2 years ago
1
Wrong operand for `vwmacc(u|us|su).vx`
#102
moimfeld
opened
2 years ago
0
Wrong result generated by multiply unit (probably control logic related)
#101
moimfeld
opened
2 years ago
1
Vicuna accepts instructions for which source registers are not valid.
#100
moimfeld
closed
2 years ago
0
`vslidedown.(vx|vi)` issue when VLMAX is exceeded
#99
moimfeld
opened
2 years ago
0
Masking not working
#98
moimfeld
opened
2 years ago
0
Tail-undisturbed policy violation for comparison instructions.
#97
moimfeld
opened
2 years ago
0
Rounding issue for `vasub(u).(vv|vx)`
#96
moimfeld
opened
2 years ago
0
Suggestion for vectorizing MaxPool and Convolution Layer
#95
Mousavikia
opened
2 years ago
1
Signal stability issue on result interface
#94
moimfeld
closed
2 years ago
4
Question about alignment and SRecord
#93
Mousavikia
closed
2 years ago
2
question about test.c
#92
schwa1z
closed
2 years ago
4
Error in Synthesizing the vicuna on Genesys2 board
#91
Nikhil-311293
opened
2 years ago
4
Asking for help about extending MEM_W to 64 bit
#90
Mousavikia
closed
2 years ago
1
Illegal configuration created by config.mk
#89
moimfeld
opened
2 years ago
2
`instr_notspec_d` signal gets updated even for illegal instructions (causing infinite stall)
#88
moimfeld
closed
2 years ago
8
Missing memory and result transaction for memory instruction
#87
moimfeld
closed
2 years ago
5
Verilator problem in simulating added custom config
#86
Mousavikia
opened
2 years ago
0
Rare infinite stall triggered by a specific delay constellation during memory transactions
#85
moimfeld
opened
2 years ago
1
Thanks for the documentation
#84
Mousavikia
closed
2 years ago
0
Missing result transaction when commit transactions are randomly delayed
#83
moimfeld
closed
2 years ago
2
Result transaction id and data issue (when `result_ready` has random delay)
#82
moimfeld
closed
2 years ago
5
vrgather.vv issue (possible control signal issue in vproc_elem)
#81
moimfeld
closed
2 years ago
3
vredsum problem even after alignment issue is solved
#80
Mousavikia
closed
2 years ago
1
Tail-agnostic policy violation for mask instruction
#79
moimfeld
opened
2 years ago
1
Adding custom configuration to config.mk file
#78
Mousavikia
closed
2 years ago
10
Bug in Verilator simulation
#77
kuoyaoming93
closed
2 years ago
3
[Question] Data cache configuration in demo_top
#76
kuoyaoming93
closed
2 years ago
2
vzext.vf2 instruction execution problem
#75
moimfeld
opened
2 years ago
4
Vector multipilication output is incorrect
#74
Mousavikia
closed
2 years ago
6
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