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vproc / vicuna

RISC-V Zve32x Vector Coprocessor
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Masking not working #98

Open moimfeld opened 2 years ago

moimfeld commented 2 years ago

Hi @michael-platzer

I remember that you told me at one point that the masking for some instructions does not work. Nevertheless I open this issue to create an overview of all instructions for which the masked version is not supported.

Issue

I have found the following instructions for which Vicuna does not support masking (i.e. Vicuna computes a wrong result if they are masked):

# All reduction instructions
vredsum.vs
vredmaxu.vs
vredmax.vs
vredminu.vs
vredmin.vs
vredand.vs
vredor.vs
vredxor.vs

# Min/Max instructions
vmin(u).(vv|vx)
vmax(u).(vv|vx)

I will extend the list if I find further instructions where the masked version is not supported. If you know some instructions where Vicuna does not support the masked version, could you please add them below.