Just like it's valuable to have the compiler synthesize higher-bit shift instructions, it's also valuable to have higher-bit increment instruction synthesized from smaller ones, eg. incrementing or decrementing a 16-bit counter counter on the 6502 can take advantage of a mix of smaller increments and branching on the zero flag at appropriate spots.
Whenever a direct instruction match for incrementation is found, still use it. But, when no such match is found, see if it is possible to decompose into smaller increments and branching.
Also, we could also toss in support for making ++ doing in clc, adc #1 shorthand for incrementing the accumulator on the stock 6502 which has no increment, but supports addition. Likewise for -- and sec, sbc #1.
Just like it's valuable to have the compiler synthesize higher-bit shift instructions, it's also valuable to have higher-bit increment instruction synthesized from smaller ones, eg. incrementing or decrementing a 16-bit counter counter on the 6502 can take advantage of a mix of smaller increments and branching on the zero flag at appropriate spots.
Whenever a direct instruction match for incrementation is found, still use it. But, when no such match is found, see if it is possible to decompose into smaller increments and branching.
Also, we could also toss in support for making
++
doing inclc, adc #1
shorthand for incrementing the accumulator on the stock 6502 which has no increment, but supports addition. Likewise for--
andsec, sbc #1
.