add initial v5 board - Githubissues

garlick commented 3 months ago

OK, here's a stab at laying out the board on the current HAT template provided in kicad 8 with the FFC cutouts. I also added cutouts for the pi5 FFCs, which were not on the template, based on the mechanical section of the HAT+ spec, and enlarged the cutout on the west end of the board so it improves ergonomics for a horizontal 26 pin header, if used.

This board uses an SMT gpio header for stacking as discussed in #67.

The GPIO pin assignments are adjusted to free up I2C, UART0, and PWM0 pins as proposed by @quorten in #64 and adds a Qwiic connector.

This board allows the vcc_cable supply to be strapped for either 5V or 3V3 as described in the SN74LVC16128 data sheet. When strapped for 3V3 it obviously should have no problem in standby mode as worried about in #66, although I think it's yet to be seen if there is any real issue when 5V is used.

Chip resistors and capacitors were shrunk from 0805 to 0603 as it tidies up the board slightly and I've found they're nearly as easy to hand solder as the 0805s. (I hope I'm not too far out in left field on that one!)

In theory this is HAT+ compatible. I want to make another pass through that document though to be sure before adding that claim to the board silkscreen.

The board is routed a little tighter. I added some silkscreen documentation to the unused areas.

Here's a preview of the board front. hat

(updated sept 2) (and again sept 7)

garlick commented 3 months ago

Fix coming for ground fill encroaching on 40-pin connector pass thru holes.

quorten commented 3 months ago

Looking pretty good! I would like to think that 0603 are still decent to handle but I haven't yet worked with them myself.

I see there are two bypass capacitors on the 3V3 side of SN74LVC16128. Reading around I see TI has that recommendation for multiple voltage input chips, that is new knowledge for me. Now I'm wondering about the 5V side, would it also be good to have two bypass capacitors there?

Of course, we know that many folks have been getting decent results on this and similar projects like RaSCSI that have been skimping on bypass capacitors. Part of the pinout design of having the power pins between the data lines helps reduce interference on its own.

garlick commented 3 months ago

Thanks! I tacked on an additional commit that adds a 1K pullup on the EEPROM WP per the HAT+ spec, then rebased on master after #69 was merged.

On the bypass caps: I have seen recommendations of one cap per supply line for microprocessors like the STM32 and I just figured it wouldn't hurt here too. I didn't add them to the 5V side because I had a vague recollection that the datasheet said not to, but skimming through it now I don't see that so maybe we should.

Edit: I don't think it hurts anyway and it might help.

garlick commented 3 months ago

Oops I had the box checked that removed footprints not present in the schematic in that last commit, which dropped the OSHW logo and DB25 pinout. Fixed that, renamed the board title to include the word HAT+ and added bypass caps on VCC_cable pins.

quorten commented 3 months ago

On the schematic, the labeling for the I2C, UART, and PWM pins, could we also note the BCM GPIO# in addition to the function? It's a nice convenience to see all the GPIO numbers in the schematic.

garlick commented 2 months ago

@quorten - I think this might be ready to go. Shall I squash some of the incremental development?

I can follow this PR with

more detailed BOM metadata
scripts to run DRC/ERC in CI wtih kicad 8

Then maybe I'll have a few boards made. I can send you a couple if you'd like to help test.

quorten commented 2 months ago

@garlick Sure, squashing the incremental development is probably good.

In the near term, I may not be able to do very demanding of a test because of ink sourcing questions on my parallel port printer. But if I get my scanner and Gameshark working from Linux, I'd be ready to test.

garlick commented 2 months ago

OK, here's a squashed version with two corrections:

I had the GPIO pin numbers flipped vertically. The footprint was numbered for being mounted on the bottom of the board and I put it on the top. Renumbered pins and rerouted. While fixing that I found a better footprint in the kicad library that has alignment holes and switched to that (actually a local copy to get the pin numbers right).
Some of the silk screen was probably not going to be readable. Using a larger size required some notes to be shortened and the copyright and URL to be moved to the back of the board.

I also updated the board picture at the top of this PR.

Let me know how it looks @quorten and please give it an approval if you think we're good to go. Thanks!

garlick commented 2 months ago

Added a small change to include the 40-pin connector area in the ground fill with 0.2mm keepouts around each NPTH. I'll squash that down once approved, before merging.

quorten commented 2 months ago

Good catch on the GPIO pin number vertical flipping. Everything looks good to me as far as I can tell.

garlick commented 2 months ago

Thanks! I squashed that one fixup commit and now I"ll merge.

worlickwerx / pi-parport

add initial v5 board #68