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wuxx / icesugar

iCESugar FPGA Board (base on iCE40UP5k)
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make gateware failed #40

Closed fatalfeel closed 2 years ago

fatalfeel commented 2 years ago

export PLATFORM=ice40_up5k_b_evn export TARGET=base export CPU=vexriscv export CPU_VARIANT=linux export FIRMWARE=linux

wget https://raw.githubusercontent.com/enjoy-digital/litex/master/litex_setup.py chmod +x ./litex_setup.py ./litex_setup.py init install --user

./scripts/debian-setup.sh ./scripts/download-env.sh

source ./scripts/enter-env.sh make gateware


#error

mkdir -p build/ice40_up5k_b_evn_base_vexriscv.linux/
time python -u ./make.py --platform=ice40_up5k_b_evn --target=base --cpu-type=vexriscv --iprange=192.168.100   --cpu-variant=linux --cpu-variant=linux  \
    2>&1 | tee -a /root/icesugar/icesugar/src/advanced/litex-buildenv/build/ice40_up5k_b_evn_base_vexriscv.linux//output.20210925-052953.log; (exit ${PIPESTATUS[0]})
Compat: SoCSDRAM is deprecated since 2020-03-24 and will soon no longer work, please update. Switch to SoCCore/add_sdram/soc_core_args instead...........thanks :)

Traceback (most recent call last):
  File "./make.py", line 169, in <module>
    main()
  File "./make.py", line 123, in main
    soc = get_soc(args, platform)
  File "./make.py", line 57, in get_soc
    soc = SoC(platform, ident=SoC.__name__, **soc_sdram_argdict(args), **dict(args.target_option))
  File "/root/icesugar/icesugar/src/advanced/litex-buildenv/targets/ice40_up5k_b_evn/base.py", line 105, in __init__
    type="cached+linker")
  File "/root/icesugar/icesugar/src/advanced/litex/litex/soc/integration/soc_core.py", line 252, in add_memory_region
    linker="linker" in type))
  File "/root/icesugar/icesugar/src/advanced/litex/litex/soc/integration/soc.py", line 166, in add_region
    raise
RuntimeError: No active exception to reraise

/////////////////////
run bootstrap.sh

ompiler_rt'...
fatal: \u7248\u672c\u5eab 'https://git.llvm.org/git/compiler-rt/' \u672a\u627e\u5230
fatal: \u7121\u6cd5\u8907\u88fd 'https://git.llvm.org/git/compiler-rt' \u5230\u5b50\u6a21\u7d44\u8def\u5f91 '/root/icesugar/icesugar/src/advanced/litex-buildenv/third_party/litex/litex/soc/software/compiler_rt'
\u8907\u88fd 'litex/soc/software/compiler_rt' \u5931\u6557\u3002\u5df2\u6392\u7a0b\u91cd\u8a66\u4f5c\u696d
\u6b63\u8907\u88fd\u5230 '/root/icesugar/icesugar/src/advanced/litex-buildenv/third_party/litex/litex/soc/software/compiler_rt'...
fatal: \u7248\u672c\u5eab 'https://git.llvm.org/git/compiler-rt/' \u672a\u627e\u5230
fatal: \u7121\u6cd5\u8907\u88fd 'https://git.llvm.org/git/compiler-rt' \u5230\u5b50\u6a21\u7d44\u8def\u5f91 '/root/icesugar/icesugar/src/advanced/litex-buildenv/third_party/litex/litex/soc/software/compiler_rt'
\u7b2c\u4e8c\u6b21\u5617\u8a66\u8907\u88fd 'litex/soc/software/compiler_rt' \u5931\u6557\uff0c\u4e2d\u6b62\u4f5c\u696d
fatal: \u7121\u6cd5\u905e\u8ff4\u9032\u5b50\u6a21\u7d44\u8def\u5f91 'third_party/litex'
////////////////////
by the way way can ice40_up5k_b_evn success run simple linux or zepyhr?
fatalfeel commented 2 years ago

fix a lot on firmware section http://fatalfeel.blogspot.com/2021/09/risc-v-on-icesugar.html

///THE success message// Info: Device utilisation: Info: ICESTORM_LC: 3074/ 5280 58% Info: ICESTORM_RAM: 6/ 30 20% Info: SB_IO: 16/ 96 16% Info: SB_GB: 8/ 8 100% Info: ICESTORM_PLL: 0/ 1 0% Info: SB_WARMBOOT: 0/ 1 0% Info: ICESTORM_DSP: 0/ 8 0% Info: ICESTORM_HFOSC: 0/ 1 0% Info: ICESTORM_LFOSC: 0/ 1 0% Info: SB_I2C: 0/ 2 0% Info: SB_SPI: 0/ 2 0% Info: IO_I3C: 0/ 2 0% Info: SB_LEDDA_IP: 0/ 1 0% Info: SB_RGBA_DRV: 0/ 1 0% Info: ICESTORM_SPRAM: 4/ 4 100%

Info: Placed 16 cells based on constraints. Info: Creating initial analytic placement for 2786 cells, random placement wirelen = 77459. Info: at initial placer iter 0, wirelen = 874 Info: at initial placer iter 1, wirelen = 766 Info: at initial placer iter 2, wirelen = 760 Info: at initial placer iter 3, wirelen = 763 Info: Running main analytical placer. Info: at iteration #1, type ALL: wirelen solved = 761, spread = 26631, legal = 34370; time = 0.15s Info: at iteration #2, type ALL: wirelen solved = 1105, spread = 20102, legal = 28226; time = 0.14s Info: at iteration #3, type ALL: wirelen solved = 1852, spread = 19291, legal = 28088; time = 0.12s Info: at iteration #4, type ALL: wirelen solved = 2563, spread = 18455, legal = 24775; time = 0.09s Info: at iteration #5, type ALL: wirelen solved = 3250, spread = 19084, legal = 24482; time = 0.09s Info: at iteration #6, type ALL: wirelen solved = 3678, spread = 18857, legal = 23250; time = 0.08s Info: at iteration #7, type ALL: wirelen solved = 5042, spread = 18204, legal = 23880; time = 0.09s Info: at iteration #8, type ALL: wirelen solved = 5492, spread = 17621, legal = 22718; time = 0.08s Info: at iteration #9, type ALL: wirelen solved = 6374, spread = 17141, legal = 22955; time = 0.08s Info: at iteration #10, type ALL: wirelen solved = 7123, spread = 16729, legal = 22393; time = 0.08s Info: at iteration #11, type ALL: wirelen solved = 7465, spread = 16548, legal = 21997; time = 0.08s Info: at iteration #12, type ALL: wirelen solved = 7917, spread = 16659, legal = 21537; time = 0.08s Info: at iteration #13, type ALL: wirelen solved = 8503, spread = 16622, legal = 21403; time = 0.08s Info: at iteration #14, type ALL: wirelen solved = 8936, spread = 16175, legal = 20985; time = 0.07s Info: at iteration #15, type ALL: wirelen solved = 9222, spread = 16264, legal = 20761; time = 0.08s Info: at iteration #16, type ALL: wirelen solved = 9645, spread = 16344, legal = 20809; time = 0.07s Info: at iteration #17, type ALL: wirelen solved = 10037, spread = 16213, legal = 20612; time = 0.07s Info: at iteration #18, type ALL: wirelen solved = 10246, spread = 15945, legal = 19911; time = 0.07s Info: at iteration #19, type ALL: wirelen solved = 10304, spread = 15819, legal = 20343; time = 0.07s Info: at iteration #20, type ALL: wirelen solved = 10618, spread = 15842, legal = 20130; time = 0.07s Info: at iteration #21, type ALL: wirelen solved = 10625, spread = 15743, legal = 20424; time = 0.07s Info: at iteration #22, type ALL: wirelen solved = 10737, spread = 15775, legal = 20490; time = 0.07s Info: at iteration #23, type ALL: wirelen solved = 10834, spread = 15662, legal = 20538; time = 0.07s Info: HeAP Placer Time: 2.50s Info: of which solving equations: 1.07s Info: of which spreading cells: 0.25s Info: of which strict legalisation: 0.74s

Info: Running simulated annealing placer for refinement. Info: at iteration #1: temp = 0.000000, timing cost = 728, wirelen = 19911 Info: at iteration #5: temp = 0.000000, timing cost = 698, wirelen = 17127 Info: at iteration #10: temp = 0.000000, timing cost = 740, wirelen = 16263 Info: at iteration #15: temp = 0.000000, timing cost = 731, wirelen = 15822 Info: at iteration #20: temp = 0.000000, timing cost = 720, wirelen = 15524 Info: at iteration #25: temp = 0.000000, timing cost = 716, wirelen = 15470 Info: at iteration #27: temp = 0.000000, timing cost = 714, wirelen = 15465 Info: SA placement time 3.45s

Info: Max frequency for clock 'clk12$SB_IOIN$glb_clk': 22.55 MHz (PASS at 12.00 MHz)

Info: Max delay -> posedge clk12$SB_IOIN$glb_clk: 10.37 ns Info: Max delay posedge clk12$SB_IOIN$glb_clk -> : 11.57 ns

Info: Slack histogram: Info: legend: * represents 10 endpoint(s) Info: + represents [1,10) endpoint(s) Info: [ 38991, 41079) |*+ Info: [ 41079, 43167) |****+ Info: [ 43167, 45255) |****+ Info: [ 45255, 47343) |*+ Info: [ 47343, 49431) |+ Info: [ 49431, 51519) |**+ Info: [ 51519, 53607) |*****+ Info: [ 53607, 55695) |****+ Info: [ 55695, 57783) |*+ Info: [ 57783, 59871) |****+ Info: [ 59871, 61959) |*+ Info: [ 61959, 64047) |***+ Info: [ 64047, 66135) |****+ Info: [ 66135, 68223) |****+ Info: [ 68223, 70311) |+ Info: [ 70311, 72399) |**** Info: [ 72399, 74487) |**+ Info: [ 74487, 76575) |*****+ Info: [ 76575, 78663) |**** Info: [ 78663, 80751) |****+ Info: Checksum: 0xc3080f4b

Info: Routing.. Info: Setting up routing queue. Info: Routing 9668 arcs. Info: | (re-)routed arcs | delta | remaining Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs Info: 1000 | 13 986 | 13 986 | 8682 Info: 2000 | 81 1918 | 68 932 | 7756 Info: 3000 | 155 2844 | 74 926 | 6850 Info: 4000 | 264 3735 | 109 891 | 6045 Info: 5000 | 384 4615 | 120 880 | 5209 Info: 6000 | 541 5458 | 157 843 | 4463 Info: 7000 | 815 6184 | 274 726 | 3867 Info: 8000 | 1143 6856 | 328 672 | 3378 Info: 9000 | 1588 7411 | 445 555 | 3006 Info: 10000 | 2028 7971 | 440 560 | 2747 Info: 11000 | 2488 8511 | 460 540 | 2548 Info: 12000 | 2875 9124 | 387 613 | 2150 Info: 13000 | 3361 9638 | 486 514 | 2017 Info: 14000 | 3807 10192 | 446 554 | 1737 Info: 15000 | 4331 10668 | 524 476 | 1654 Info: 16000 | 4843 11156 | 512 488 | 1570 Info: 17000 | 5295 11704 | 452 548 | 1375 Info: 18000 | 5786 12213 | 491 509 | 1168 Info: 19000 | 6261 12738 | 475 525 | 923 Info: 20000 | 6576 13423 | 315 685 | 441 Info: 20748 | 6728 14020 | 152 597 | 0 Info: Routing complete. Info: Route time 8.78s Info: Checksum: 0x98f344cf

Info: Critical path report for clock 'clk12$SB_IOIN$glb_clk' (posedge -> posedge): Info: curr total Info: 1.4 1.4 Source VexRiscv.decode_to_execute_SRC2_CTRL_SB_DFFE_Q_1_DFFLC.O Info: 1.8 3.2 Net VexRiscv._zz_execute_SRC2_CTRL[0] budget 3.114000 ns (12,14) -> (12,13) Info: Sink VexRiscv._zz_execute_SrcPlugin_addSub_3_SB_LUT4_O_31_I3_SB_LUT4_O_I1_SB_LUT4_O_LC.I0 Info: 1.3 4.4 Source VexRiscv._zz_execute_SrcPlugin_addSub_3_SB_LUT4_O_31_I3_SB_LUT4_O_I1_SB_LUT4_O_LC.O Info: 1.8 6.2 Net VexRiscv._zz_execute_SrcPlugin_addSub_3_SB_LUT4_O_31_I3_SB_LUT4_O_I1 budget 2.894000 ns (12,13) -> (11,13) Info: Sink VexRiscv._zz_execute_SrcPlugin_addSub_3_SB_LUT4_O_31_I3_SB_LUT4_O_LC.I1 Info: 1.2 7.4 Source VexRiscv._zz_execute_SrcPlugin_addSub_3_SB_LUT4_O_31_I3_SB_LUT4_O_LC.O Info: 4.1 11.6 Net VexRiscv._zz_execute_SrcPlugin_addSub_3_SB_LUT4_O_31_I3 budget 3.114000 ns (11,13) -> (10,21) Info: Sink VexRiscv._zz_execute_SrcPlugin_addSub_3_SB_LUT4_O_31_LC.I3 Info: 0.9 12.4 Source VexRiscv._zz_execute_SrcPlugin_addSub_3_SB_LUT4_O_31_LC.O Info: 1.8 14.2 Net VexRiscv._zz_execute_SrcPlugin_addSub_3[0] budget 3.114000 ns (10,21) -> (10,22) Info: Sink VexRiscv.dBus_cmd_payload_address_SB_LUT4_O_30_LC.I2 Info: 0.6 14.8 Source VexRiscv.dBus_cmd_payload_address_SB_LUT4_O_30_LC.COUT Info: 0.7 15.5 Net VexRiscv.decode_to_execute_SRC_USE_SUB_LESS_SB_CARRY_I0_CO[1] budget 0.660000 ns (10,22) -> (10,22) Info: Sink VexRiscv.dBus_cmd_payload_address_SB_LUT4_O_19_LC.I3 Info: 0.9 16.4 Source VexRiscv.dBus_cmd_payload_address_SB_LUT4_O_19_LC.O Info: 3.1 19.4 Net VexRiscv.dBus_cmd_payload_address[1] budget 3.114000 ns (10,22) -> (9,16) Info: Sink VexRiscv.execute_ALIGNEMENT_FAULT_SB_LUT4_O_LC.I3 Info: 0.9 20.3 Source VexRiscv.execute_ALIGNEMENT_FAULT_SB_LUT4_O_LC.O Info: 1.8 22.0 Net VexRiscv.execute_ALIGNEMENT_FAULT budget 3.114000 ns (9,16) -> (8,15) Info: Sink VexRiscv.execute_ALIGNEMENT_FAULT_SB_LUT4_I3_LC.I3 Info: 0.9 22.9 Source VexRiscv.execute_ALIGNEMENT_FAULT_SB_LUT4_I3_LC.O Info: 1.8 24.7 Net VexRiscv.execute_ALIGNEMENT_FAULT_SB_LUT4_I3_O budget 3.114000 ns (8,15) -> (8,15) Info: Sink VexRiscv.execute_ALIGNEMENT_FAULT_SB_LUT4_I3_O_SB_LUT4_I3_LC.I3 Info: 0.9 25.6 Source VexRiscv.execute_ALIGNEMENT_FAULT_SB_LUT4_I3_O_SB_LUT4_I3_LC.O Info: 1.8 27.3 Net VexRiscv.execute_ALIGNEMENT_FAULT_SB_LUT4_I3_O_SB_LUT4_I3_O budget 3.114000 ns (8,15) -> (8,14) Info: Sink VexRiscv.dBus_cmd_rData_wr_SB_LUT4_I2_1_O_SB_LUT4_I0_LC.I1 Info: 1.2 28.5 Source VexRiscv.dBus_cmd_rData_wr_SB_LUT4_I2_1_O_SB_LUT4_I0_LC.O Info: 3.0 31.5 Net VexRiscv.dBus_cmd_rData_wr_SB_LUT4_I2_1_O_SB_LUT4_I0_O budget 3.113000 ns (8,14) -> (5,12) Info: Sink VexRiscv._zz_IBusSimplePlugin_iBusRsp_stages_0_output_ready_2_SB_LUT4_I0_O_SB_LUT4_I1_LC.I3 Info: 0.9 32.4 Source VexRiscv._zz_IBusSimplePlugin_iBusRsp_stages_0_output_ready_2_SB_LUT4_I0_O_SB_LUT4_I1_LC.O Info: 1.8 34.1 Net VexRiscv._zz_IBusSimplePlugin_iBusRsp_stages_0_output_ready_2_SB_LUT4_I0_O_SB_LUT4_I1_O budget 3.113000 ns (5,12) -> (4,12) Info: Sink VexRiscv.IBusSimplePlugin_rspJoin_rspBuffer_discardCounter_SB_DFFSR_Q_2_D_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_O_LC.I3 Info: 0.9 35.0 Source VexRiscv.IBusSimplePlugin_rspJoin_rspBuffer_discardCounter_SB_DFFSR_Q_2_D_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_O_LC.O Info: 1.8 36.8 Net VexRiscv.IBusSimplePlugin_rspJoin_rspBuffer_discardCounter_SB_DFFSR_Q_2_D_SB_LUT4_O_I3_SB_LUT4_O_I2 budget 3.113000 ns (4,12) -> (4,12) Info: Sink VexRiscv.IBusSimplePlugin_rspJoin_rspBuffer_discardCounter_SB_DFFSR_Q_2_D_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_CARRY_I1$CARRY.I2 Info: 0.6 37.4 Source VexRiscv.IBusSimplePlugin_rspJoin_rspBuffer_discardCounter_SB_DFFSR_Q_2_D_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_CARRY_I1$CARRY.COUT Info: 0.0 37.4 Net VexRiscv.IBusSimplePlugin_rspJoin_rspBuffer_discardCounter_SB_DFFSR_Q_2_D_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_CARRY_I1_CO[1] budget 0.000000 ns (4,12) -> (4,12) Info: Sink VexRiscv.IBusSimplePlugin_rspJoin_rspBuffer_discardCounter_SB_DFFSR_Q_1_D_SB_LUT4_O_I3_SB_LUT4_O_LC.CIN Info: 0.3 37.7 Source VexRiscv.IBusSimplePlugin_rspJoin_rspBuffer_discardCounter_SB_DFFSR_Q_1_D_SB_LUT4_O_I3_SB_LUT4_O_LC.COUT Info: 0.7 38.3 Net VexRiscv.IBusSimplePlugin_rspJoin_rspBuffer_discardCounter_SB_DFFSR_Q_2_D_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_CARRY_I1_CO[2] budget 0.660000 ns (4,12) -> (4,12) Info: Sink VexRiscv.IBusSimplePlugin_rspJoin_rspBuffer_discardCounter_SB_DFFSR_Q_D_SB_LUT4_O_I2_SB_LUT4_O_LC.I3 Info: 0.9 39.2 Source VexRiscv.IBusSimplePlugin_rspJoin_rspBuffer_discardCounter_SB_DFFSR_Q_D_SB_LUT4_O_I2_SB_LUT4_O_LC.O Info: 1.8 40.9 Net VexRiscv.IBusSimplePlugin_rspJoin_rspBuffer_discardCounter_SB_DFFSR_Q_D_SB_LUT4_O_I2 budget 14.214000 ns (4,12) -> (4,11) Info: Sink VexRiscv.IBusSimplePlugin_rspJoin_rspBuffer_discardCounter_SB_DFFSR_Q_D_SB_LUT4_O_LC.I2 Info: 1.2 42.1 Setup VexRiscv.IBusSimplePlugin_rspJoin_rspBuffer_discardCounter_SB_DFFSR_Q_D_SB_LUT4_O_LC.I2 Info: 14.8 ns logic, 27.3 ns routing

Info: Critical path report for cross-domain path '' -> 'posedge clk12$SB_IOIN$glb_clk': Info: curr total Info: 0.0 0.0 Source spiflash_miso$sb_io.D_IN_0 Info: 6.4 6.4 Net spiflash_miso$SB_IO_IN budget 40.382000 ns (23,0) -> (3,9) Info: Sink spiflash_miso_SB_LUT4_I0_LC.I0 Info: 1.3 7.7 Source spiflash_miso_SB_LUT4_I0_LC.O Info: 1.8 9.5 Net spiflash_miso_SB_LUT4_I0_O budget 10.643000 ns (3,9) -> (3,9) Info: Sink csrbankarray_interface2_bank_bus_dat_r_SB_DFFSR_Q_3_D_SB_LUT4_O_LC.I2 Info: 1.2 10.6 Setup csrbankarray_interface2_bank_bus_dat_r_SB_DFFSR_Q_3_D_SB_LUT4_O_LC.I2 Info: 2.4 ns logic, 8.2 ns routing

Info: Critical path report for cross-domain path 'posedge clk12$SB_IOIN$glb_clk' -> '': Info: curr total Info: 1.4 1.4 Source spiflash_bitbang_en_storage_SB_DFFESR_Q_DFFLC.O Info: 5.2 6.6 Net csrbankarray_csrbank2_bitbang_en0_w budget 39.164001 ns (1,9) -> (14,2) Info: Sink spiflash_cs_n_SB_LUT4_O_LC.I1 Info: 1.2 7.8 Source spiflash_cs_n_SB_LUT4_O_LC.O Info: 4.1 12.0 Net spiflash_cs_n$SB_IO_OUT budget 39.376999 ns (14,2) -> (24,0) Info: Sink spiflash_cs_n$sb_io.D_OUT_0 Info: 2.6 ns logic, 9.4 ns routing

Info: Max frequency for clock 'clk12$SB_IOIN$glb_clk': 23.75 MHz (PASS at 12.00 MHz)

Info: Max delay -> posedge clk12$SB_IOIN$glb_clk: 10.62 ns Info: Max delay posedge clk12$SB_IOIN$glb_clk -> : 11.99 ns

Info: Slack histogram: Info: legend: represents 10 endpoint(s) Info: + represents [1,10) endpoint(s) Info: [ 41229, 43205) |+ Info: [ 43205, 45181) |**+ Info: [ 45181, 47157) |****+ Info: [ 47157, 49133) |*****+ Info: [ 49133, 51109) |*+ Info: [ 51109, 53085) |*+ Info: [ 53085, 55061) |**+ Info: [ 55061, 57037) |****+ Info: [ 57037, 59013) |*****+ Info: [ 59013, 60989) |**+ Info: [ 60989, 62965) |****+ Info: [ 62965, 64941) |**+ Info: [ 64941, 66917) |**+ Info: [ 66917, 68893) |*+ Info: [ 68893, 70869) |**** Info: [ 70869, 72845) |**+ Info: [ 72845, 74821) |**+ Info: [ 74821, 76797) |***+ Info: [ 76797, 78773) |****+ Info: [ 78773, 80749) |****+

real 0m29.493s user 0m30.073s sys 0m0.503s (LX P=ice40_up5k_b_evn C=vexriscv F=linux R=???) root@homelinux:~/icesugar/icesugar/src/advanced/litex-buildenv#