VCS lint issue in br_counter.sv

xlsynth / bedrock-rtl

High quality and composable base RTL libraries in SystemVerilog

Apache License 2.0

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VCS lint issue in br_counter.sv #200

Closed mgottscho closed 1 week ago

mgottscho commented 1 week ago

VCS caught a lint issue of continuous assignment width mismatch in br_counter. This is caught in VCS when all lint warnings are elevated to full-blown errors.

Next steps:

Fix the lib
Understand why verilog_lint_test doesn't catch it
Consider elevating all lint warnings in verilog_sim_test to be errors.

Found by @awijaya-openai

mgottscho commented 1 week ago

Lib was fixed in #197.

Filed internal issues on tooling so this doesn't escape these unit tests in the future.