xlsynth / bedrock-rtl

High quality and composable base RTL libraries in SystemVerilog
Apache License 2.0
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Fix some issues with br_fifo_test_harness and use for push credit test #211

Closed zhemao-openai closed 3 days ago

zhemao-openai commented 4 days ago
  1. The handling of negedge/posedge in the testbench could cause some spurious simulation failures. This change makes things more consistent.
  2. Use the br_fifo_test_harness to check br_fifo_flops_push_credit. The Depth needs to be adjusted to allow full throughput as the test harness expects.
  3. Make sure the timeout counter is actually decrementing.

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