SECDED ECC does not balance rows of parity check matrix

xlsynth / bedrock-rtl

High quality and composable base RTL libraries in SystemVerilog

Apache License 2.0

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SECDED ECC does not balance rows of parity check matrix #220

Open mgottscho opened 3 days ago

mgottscho commented 3 days ago

SECDED ECC codes seem to work correctly but they don't balance the logic depth and minimize the number of XOR gates as optimally as a Hsiao code should. Check out the python script and figure out what change is needed.