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yupferris / kaze

An HDL embedded in Rust.
Apache License 2.0
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test trace_test_module_2 failed: panicked at 'assertion failed: `(left == right)` #39

Open Boscop opened 1 year ago

Boscop commented 1 year ago

Thanks for making this crate, it seems very useful to get into hardware design.

I just cloned this repo and ran the tests, one test failed:

test tests::trace_test_module_2 ... FAILED

failures:

---- tests::trace_test_module_2 stdout ----
thread 'tests::trace_test_module_2' panicked at 'assertion failed: `(left == right)`
  left: `module trace_test_module_2:
    children:
        module inner1:
            children:
            signals:
                i1: 32 bit(s) (U32)
                    0: U32(0)
                    0: U32(4294967295)
                    1: U32(4294967295)
                    2: U32(4294967295)
                i2: 32 bit(s) (U32)
                    0: U32(0)
                    0: U32(4294901760)
                    1: U32(4294901760)
                    2: U32(4294901760)
                o: 32 bit(s) (U32)
                    0: U32(0)
                    0: U32(0)
                    1: U32(4294901760)
                    2: U32(4294901760)
                r: 32 bit(s) (U32)
                    0: U32(0)
                    0: U32(0)
                    1: U32(4294901760)
                    2: U32(4294901760)
        module inner2:
            children:
            signals:
                i1: 32 bit(s) (U32)
                    0: U32(0)
                    0: U32(16711680)
                    1: U32(16711680)
                    2: U32(16711680)
                i2: 32 bit(s) (U32)
                    0: U32(0)
                    0: U32(983040)
                    1: U32(983040)
                    2: U32(983040)
                o: 32 bit(s) (U32)
                    0: U32(0)
                    0: U32(0)
                    1: U32(983040)
                    2: U32(983040)
                r: 32 bit(s) (U32)
                    0: U32(0)
                    0: U32(0)
                    1: U32(983040)
                    2: U32(983040)
        module inner3:
            children:
            signals:
                i1: 32 bit(s) (U32)
                    0: U32(0)
                    0: U32(0)
                    1: U32(4294901760)
                    2: U32(4294901760)
                i2: 32 bit(s) (U32)
                    0: U32(0)
                    0: U32(0)
                    1: U32(983040)
                    2: U32(983040)
                o: 32 bit(s) (U32)
                    0: U32(0)
                    0: U32(0)
                    1: U32(0)
                    2: U32(983040)
                r: 32 bit(s) (U32)
                    0: U32(0)
                    0: U32(0)
                    1: U32(0)
                    2: U32(983040)
    signals:
        i1: 32 bit(s) (U32)
            0: U32(0)
            0: U32(4294967295)
            1: U32(4294967295)
            2: U32(4294967295)
        i2: 32 bit(s) (U32)
            0: U32(0)
            0: U32(4294901760)
            1: U32(4294901760)
            2: U32(4294901760)
        i3: 32 bit(s) (U32)
            0: U32(0)
            0: U32(16711680)
            1: U32(16711680)
            2: U32(16711680)
        i4: 32 bit(s) (U32)
            0: U32(0)
            0: U32(983040)
            1: U32(983040)
            2: U32(983040)
        o: 32 bit(s) (U32)
            0: U32(0)
            0: U32(0)
            1: U32(0)
            2: U32(983040)
`,
 right: `module trace_test_module_2:
    children:
        module inner1:
            children:
            signals:
                r: 32 bit(s) (U32)
                    0: U32(0)
                    0: U32(0)
                    1: U32(4294901760)
                    2: U32(4294901760)
        module inner2:
            children:
            signals:
                r: 32 bit(s) (U32)
                    0: U32(0)
                    0: U32(0)
                    1: U32(983040)
                    2: U32(983040)
        module inner3:
            children:
            signals:
                r: 32 bit(s) (U32)
                    0: U32(0)
                    0: U32(0)
                    1: U32(0)
                    2: U32(983040)
    signals:
        i1: 32 bit(s) (U32)
            0: U32(0)
            0: U32(4294967295)
            1: U32(4294967295)
            2: U32(4294967295)
        i2: 32 bit(s) (U32)
            0: U32(0)
            0: U32(4294901760)
            1: U32(4294901760)
            2: U32(4294901760)
        i3: 32 bit(s) (U32)
            0: U32(0)
            0: U32(16711680)
            1: U32(16711680)
            2: U32(16711680)
        i4: 32 bit(s) (U32)
            0: U32(0)
            0: U32(983040)
            1: U32(983040)
            2: U32(983040)
        o: 32 bit(s) (U32)
            0: U32(0)
            0: U32(0)
            1: U32(0)
            2: U32(983040)
`', sim-tests\src\lib.rs:2378:9
stack backtrace:
   0: std::panicking::begin_panic_handler
             at /rustc/ec2f40c6b04f0e9850dd1f454e8639d319f4ed9b/library\std\src\panicking.rs:577
   1: core::panicking::panic_fmt
             at /rustc/ec2f40c6b04f0e9850dd1f454e8639d319f4ed9b/library\core\src\panicking.rs:67
   2: core::fmt::Arguments::new_v1
             at /rustc/ec2f40c6b04f0e9850dd1f454e8639d319f4ed9b/library\core\src\fmt\mod.rs:416
   3: core::panicking::assert_failed_inner
             at /rustc/ec2f40c6b04f0e9850dd1f454e8639d319f4ed9b/library\core\src\panicking.rs:260
   4: core::panicking::assert_failed<sim_tests::tests::Capture,sim_tests::tests::Capture>
             at /rustc/ec2f40c6b04f0e9850dd1f454e8639d319f4ed9b\library\core\src\panicking.rs:214
   5: sim_tests::tests::trace_test_module_2
             at .\src\lib.rs:2378
   6: sim_tests::tests::trace_test_module_2::closure$0
             at .\src\lib.rs:2346
   7: core::ops::function::FnOnce::call_once<sim_tests::tests::trace_test_module_2::closure_env$0,tuple$<> >
             at /rustc/ec2f40c6b04f0e9850dd1f454e8639d319f4ed9b\library\core\src\ops\function.rs:250
   8: core::ops::function::FnOnce::call_once
             at /rustc/ec2f40c6b04f0e9850dd1f454e8639d319f4ed9b/library\core\src\ops\function.rs:250
note: Some details are omitted, run with `RUST_BACKTRACE=full` for a verbose backtrace.

failures:
    tests::trace_test_module_2

test result: FAILED. 44 passed; 1 failed; 0 ignored; 0 measured; 0 filtered out; finished in 0.03s

error: test failed, to rerun pass `--lib`

https://github.com/yupferris/kaze/blob/adc8f3f75cfc0a32e96d6d401389673e48a3b126/sim-tests/src/lib.rs#L2378

Diff between lhs and rhs of the assert: https://www.diffchecker.com/Oh4K0ECz/

yupferris commented 1 year ago

Thanks for reporting. This is known and will be fixed (sometime?) before the next versioned release. I'll keep this issue open for tracking purposes.