Open mobeen10x opened 10 months ago
After knowing more about bugs :
Issue Title: Incorrect Output in Sampling Module1
During the testing of Sampling Module1, the 74th and last output do not match the expected results. Specifically, the 74th output consistently shows 'hffff' for all inputs, and the last output is also incorrect.
The output of the DUT (Design Under Test) should match the Reference Model Output. This discrepancy in the 74th and last output is unexpected, as all other 142 outputs match the Reference Model.
The issue appears to be related to the typo error.
'd004: Output_Pixel <= (Latch_Buffer[288+04] + Latch_Buffer[288+05] + Latch_Buffer[288+28] + Latch_Buffer[288+29]) /4;( design code line number 223)
in the place of assigning the 74th value there is a typo, So for the 74th value output is hffff because the default value of the case is hffff.
To resolve this issue, you can consider the following possible solutions: Replace the upper code of the line with
'd074: Output_Pixel <= (Latch_Buffer[288+04] + Latch_Buffer[288+05] + Latch_Buffer[288+28] + Latch_Buffer[288+29]) /4;
The issue appears to be related to Input_Buffer not getting the last value of the input matrix.
if (Input_Counter == 575)
begin
Flag_Input_Buffer_Filled <= 'b1;
end
else if (Input_Counter < 575)
begin
Input_Buffer[Input_Counter] <= Input_Pixel;
Input_Counter <= Input_Counter + 1;
end
Here 575th input is never going to be registered in buffer.
To resolve this issue, you can consider the following possible solutions: Replace the upper code of the line with
if (Input_Counter < 576)
begin
Input_Buffer[Input_Counter] <= Input_Pixel;
Input_Counter <= Input_Counter + 1;
if(Input_Counter == 575)
begin
Flag_Input_Buffer_Filled <= 'b1;
end
end
end
To reproduce this issue, follow these steps:
make rerun
.The 74th output consistently displays 'hffff' for all inputs, and the last output is incorrect.
After running make rerun
, the output.txt
file will be updated with the output of the Verification Environment. You can search for Test: Fail!
in this file, and both failed tests will be highlighted with a Driven 4x4 matrix.
The Verification Environment is responsible for driving stimulus to the Module and then comparing the DUT Results with the Results of the Reference Model in the Scoreboard.
To simulate this environment, you will need a UVM-enabled simulator. The author used Synopsys VCS Version L-2016.06_Full64 for this verification.
Please file the second issue separately.
Issue Title
The 74th and last output of Sampling Module1 is not correct.
Description
Problem Description
During Testing of Sampling Module 1 74th and last output is not correct all remaining 142 outputs are correct.
Expected Behavior
DUT output should be match with Reference Model Output because all other 142 outputs are same with Reference Model.
Current Behavior
74th Output is 'hffff for all inputs and last output is not 'hffff but incorrect.
Reproduction Steps
make rerun
Output of Environment
After Running
make rerun
output.txt file will be updated and the Output of Verification Environment will be in it. You can search forTest: Fail!
Both Failed tests will be highlighted with Drived 4x4 matrix.Environment Details
Verification Environment is Driving Stimulus to Module and then Comparing DUT Results with Results of Reference Model in Scoreboard.
Requirements For Simulation
UVM Enabled Simulator is Required I am Using Synopsys VCS Version L-2016.06_Full64