VM2 SEL274

[xolod79]

When the VIRQ request does not acknowledge the interrupt vector, interrupts should occur at address SEL274, but the usual interrupt 004 occurs. Analysis of the problem showed that the reason is that the pli_ack signal is one clock cycle behind p[6] = acin & qbto & iako. It seems that this happened when switching to a synchronous processor model. This is not a problem at the DVK and UKNC, but it is critical for the work of the Souyz Neon. I made a workaround by delaying the end of the wbi_stb_o signal by one clock cycle, but I’m not sure that this is the best solution.

+reg   old_wbi_stb_o;

always @(posedge vm_clk_p)
begin
+  old_wbi_stb_o <= wbi_stb_o;
-   vec_stb <= wbi_stb_o & ~wbi_una_o; 
+  vec_stb <= (wbi_stb_o | (old_wbi_stb_o & ~wbi_stb_o )) & ~wbi_una_o;

[1801BM1]

Thank you for the comprehensive issue description, will handle.

[1801BM1]

The fix pushed: https://github.com/1801BM1/cpu11/commit/2f765b4f632b3d9ce43a556e5d36b53776963bea

[xolod79]

I checked it on FPGAs Soyuz Neone, it works fine.

[1801BM1]

I checked it on FPGAs Soyuz Neone, it works fine.

OK, thank you