Work around for Xcode 4.4

[GoogleCodeExporter]

What steps will reproduce the problem?
1. Xcode build

What is the expected output? What do you see instead?
Expect no errors.
Compiling scale.cc produces 3 identical errors on vqrdmulh.s16 instructions:
Inline Assembly Issue
Invalid operation for instruction

What version of the product are you using? On what operating system?
libyuv r324
OS X 10.7.4
Xcode 4.4.1

Please provide any additional information below.

Compiler does not seem to recognize that these instructions may have an 
optional destination register. The easy work around seems to be to add the 
first source register as the explicit destination register.

See the attached diff file.

Original issue reported on code.google.com by ma...@bluejeansnet.com on 22 Aug 2012 at 10:17

Attachments:

• scale.cc.diff

[GoogleCodeExporter]

I forgot to mention that armv7 is the target for the build - Mark

Original comment by ma...@bluejeansnet.com on 22 Aug 2012 at 11:33

[GoogleCodeExporter]

Thanks for your detailed report/fix!  It must be a clang vs gcc compatibility 
thing.
Fix looks good.

--- scale.cc    2012-08-22 14:49:55.000000000 -0700
+++ scale.cc.fixed  2012-08-22 14:41:22.000000000 -0700
@@ -357,7 +357,7 @@
     // dst_ptr[3] = (s[6 + st * 0] + s[7 + st * 0]
     //             + s[6 + st * 1] + s[7 + st * 1]
     //             + s[6 + st * 2] + s[7 + st * 2]) / 6
-    "vqrdmulh.s16 q2, q13                      \n"
+    "vqrdmulh.s16 q2, q2, q13                  \n"
     "vmovn.u16    d4, q2                       \n"

     // Shuffle 2,3 reg around so that 2 can be added to the
@@ -388,7 +388,7 @@
     // Need to divide, but can't downshift as the the value
     //  isn't a power of 2.  So multiply by 65536 / n
     //  and take the upper 16 bits.
-    "vqrdmulh.s16 q0, q15                      \n"
+    "vqrdmulh.s16 q0, q0, q15                  \n"

     // Align for table lookup, vtbl requires registers to
     //  be adjacent
@@ -484,7 +484,7 @@
     // Need to divide, but can't downshift as the the value
     //  isn't a power of 2.  So multiply by 65536 / n
     //  and take the upper 16 bits.
-    "vqrdmulh.s16 q0, q13                      \n"
+    "vqrdmulh.s16 q0, q0, q13                  \n"

     // Align for table lookup, vtbl requires registers to
     //  be adjacent

Original comment by fbarch...@google.com on 23 Aug 2012 at 3:33

• Changed state: Accepted

[GoogleCodeExporter]

Fixed in r325.

Original comment by fbarch...@google.com on 23 Aug 2012 at 4:18

• Changed state: Fixed