Closed GoogleCodeExporter closed 9 years ago
I forgot to mention that armv7 is the target for the build - Mark
Original comment by ma...@bluejeansnet.com
on 22 Aug 2012 at 11:33
Thanks for your detailed report/fix! It must be a clang vs gcc compatibility
thing.
Fix looks good.
--- scale.cc 2012-08-22 14:49:55.000000000 -0700
+++ scale.cc.fixed 2012-08-22 14:41:22.000000000 -0700
@@ -357,7 +357,7 @@
// dst_ptr[3] = (s[6 + st * 0] + s[7 + st * 0]
// + s[6 + st * 1] + s[7 + st * 1]
// + s[6 + st * 2] + s[7 + st * 2]) / 6
- "vqrdmulh.s16 q2, q13 \n"
+ "vqrdmulh.s16 q2, q2, q13 \n"
"vmovn.u16 d4, q2 \n"
// Shuffle 2,3 reg around so that 2 can be added to the
@@ -388,7 +388,7 @@
// Need to divide, but can't downshift as the the value
// isn't a power of 2. So multiply by 65536 / n
// and take the upper 16 bits.
- "vqrdmulh.s16 q0, q15 \n"
+ "vqrdmulh.s16 q0, q0, q15 \n"
// Align for table lookup, vtbl requires registers to
// be adjacent
@@ -484,7 +484,7 @@
// Need to divide, but can't downshift as the the value
// isn't a power of 2. So multiply by 65536 / n
// and take the upper 16 bits.
- "vqrdmulh.s16 q0, q13 \n"
+ "vqrdmulh.s16 q0, q0, q13 \n"
// Align for table lookup, vtbl requires registers to
// be adjacent
Original comment by fbarch...@google.com
on 23 Aug 2012 at 3:33
Fixed in r325.
Original comment by fbarch...@google.com
on 23 Aug 2012 at 4:18
Original issue reported on code.google.com by
ma...@bluejeansnet.com
on 22 Aug 2012 at 10:17Attachments: