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360nosc0pe / scope

Siglent SDS1x0xX-E FPGA bitstreams
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Add overflow detection on ADC's source to be sure the DRAM can keep up. #1

Closed enjoy-digital closed 3 years ago

enjoy-digital commented 3 years ago

When capturing ADC's data to the DRAM, we want to be sure the DRAM is able to keep up with the incoming data stream. Adding an overflow detection on ADC's source will provide this information and will also help finding the optimal FIFO's depths.

The DRAM should accept up to 20GBps with a sys_clk of 100MHz. Each ADC can generate up to 8Gbps at 1GSa/s, so a total of 16Gbps.

enjoy-digital commented 3 years ago

Min/Max registers have been added to the HAD1511 core which allow detecting Min/Max saturation.