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Siglent SDS1x0xX-E FPGA bitstreams
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Allow capturing the 4 channels simultaneously. #11

Closed enjoy-digital closed 3 years ago

enjoy-digital commented 3 years ago

It's already possible to capture the 4 channels separately and the FPGA architecture should already allow capturing the 4 channels simultaneously (with 1 DMA per ADC). The current limitation is in the python driver used to configure/trigger the capture. Minor modification to the FPGA will still probably be start the captures on the two ADCs synchronously.

enjoy-digital commented 3 years ago

This is now implemented.