The LiteX's crossover UART is handling back-pressure and then stalls the CPU when the UART FIFO is full. User currently has to connect with litex_term bridge over Etherbone to let the CPU run the BIOS and initialize the DRAM.
As already discussed in LiteX, we could add a mechanism to detect this and release the UART when ready hasn't been detected for a long time to allow the CPU to execute the BIOS.
enjoy-digital
commented
3 years ago
The LiteX's crossover UART is handling back-pressure and then stalls the CPU when the UART FIFO is full. User currently has to connect with litex_term bridge over Etherbone to let the CPU run the BIOS and initialize the DRAM.
As already discussed in LiteX, we could add a mechanism to detect this and release the UART when ready hasn't been detected for a long time to allow the CPU to execute the BIOS.