Closed enjoy-digital closed 3 years ago
Initial support for the second ADC has been added but capture data does not seem correct. There is probably a mismatch with the AFE configuration.
Is this issue suitable for Open Source? If so, could I help with it?
@diogolopes18-cyber: Yes sure, to investigate this I would first recommend reproducing the results with channel1, then maybe try to understand what is wrong with channel3 (should operate similarly to channel1). Once the two ADCs are working, we could enable the 2 channels per ADC.
@diogolopes18-cyber: Yes sure, to investigate this I would first recommend reproducing the results with channel1, then maybe try to understand what is wrong with channel3 (should operate similarly to channel1). Once the two ADCs are working, we could enable the 2 channels per ADC.
Ok, maybe I'll take a look at the electrical architecture as well. I'll try from there reproduce both results.
@diogolopes18-cyber: The issue for the second ADC was just a bad SPI_CS indexing that has been fixed with https://github.com/360nosc0pe/scope/commit/5d4d18108ae8e49eeb39727df956c9539f5ba3bc. I also added support for the second channel of each ADC with https://github.com/360nosc0pe/scope/commit/cba955c464c50b3afd6b81d91b7df0c72c63ae63. So we can now use the 4 channels separately, the FPGA should already support capturing the 4 channels simultaneously, but the software needs to be reworked a bit. Thanks for the proposed help, sorry for fixing this before allowing you to have a look but this was just a stupid error on my side and there will be lots of other things to look at if you are interested by the project :)
Now implemented.
This should be mostly a matter of configuring the ADC/Frontend/VGAs/Gains correctly and figuring out the data order at the output of the ADC.