danngreen
commented
2 years ago The GICD and GICC registers can be set up by the functions in the CMSIS library in this file: core_ca.h. If you want to see exactly what registers are being set, it's easy to see in this file. But I'd recommend using these functions rather than setting the registers yourself (less chance for error).
Generally, to setup the GICD and GICC for both cores, first you would first call GIC_Enable() from core 0 to setup the GICD (which is common to both cores) and GICC for core 0. In the multicore_a7 example project, core 0 calls SystemInit() from within startup.s. SystemInit() is in shared/system/system_ca7.c. This function sets up the FPU and MMU and other things, and calls IRQ_Initialize() which is what calls GIC_Enable().
Once the GIC is enabled by core 0, you can use core 0 to wake-up core 1. You have to follow the "magic-number" procedure that the multicore_a7 example project uses. The SecondaryCore class here makes it easy. You just need to call SecondaryCore::start() from core 0. You also have to provide a function named aux_core_main() for core 1 to start running.
For SecondaryCore::start() to work, you need to use the startup.s file in the multicore_a7 project. The section of this file that's important for core 1 is aux_core_start. This is where core 1 will branch after you call SecondaryCore::start(). Notice that aux_core_start directs core 1 to SystemInitAuxCore() (as opposed to core 0 which callsSystemInit()). The aux core version of SystemInit is almost identical to the core 0 version except that it calls GIC_CPUInterfaceInit() instead of GIC_Enable(). This function just sets up the GICC for core 1, and doesn't setup the GICD (since core 0 already set that up).
At this point, core 1 will be running whatever code you have inaux_core_main(). If you want to continue interacting with core 1 from core 0, the easiest thing is to do something like this in aux_core_main():
extern "C" void aux_core_main() {
while (true) {
// go to sleep until we get an interrupt (SGI from core0)
__DSB();
__WFI();
auto irqnum = GIC_AcknowledgePending();
GIC_EndInterrupt(irqnum);
// Do something now that we're woken up
if (irqnum == SGI0_IRQn)
do_something();
if (irqnum == SGI1_IRQn)
do_something_else();
}
}You can have core 1 do different things, depending on which number SGI you send from core 0. You also can pass data, by having Core 0 write to a specific address in memory, and then calling the SGI. Core 1 would then read from that address. Concurrency is an issue, you have to make sure you're not writing and reading at the same time (or writing the same address from two different cores). Concurrency is a huge topic, there are many established techniques for handling these issues.
Now, my questions for you:
Are you able to compile and run the projects in examples/basic_irq and examples/nested_irq, and they run ok (correct output from the UART)? Does the multicore_a7 project compile for you? If not, can you give me the exact error you're getting?
Srikanth412
Hi, I am very new to the Cortex A7 series micro processors . I can able build the simple interfaces like UART , GPIO etc . But now i am having the trouble with interrupt handling. I can able to trigger the second A7 core . I want to interact with the second A7 core's in the stm32mp157 through the software generated interrupts(means core 0 to core 1). for this how to handle the software interrupts i am unable to understand . I had tried by enabling the GICD and GICD blocks using the registers setting. I had seen the code in the git hub to control the interrupts. if i am trying the compile with Segger embedded studio ide lot errors we are facing . I need what is registers settings we need to set for the GIC and GICD both please help us in this regards.