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4ms / stm32mp1-baremetal

Baremetal framework and example projects for the STM32MP15x Cortex-A7 based MPU
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DDR3L memory #4

Closed Staringlizard closed 3 years ago

Staringlizard commented 3 years ago

Nice work, and thanks for making this available! Just a quick question about the RAM that I often see on the MP1 dev boards from ST. Is the RAM available and controlled automatically, or is this something that needs to be done to get that up and running?

danngreen commented 3 years ago

Thanks!

Yes, the DDR3 RAM needs to be initialized. Once it's up and running you can access it like any other RAM.

In this project, U-boot does the initialization. It's required to be done early in the startup process because the ROM bootloader is hard-coded to load just a small bit of code called the first-stage bootloader (FSBL) from the SD card (or from other sources, depending on the BOOT pins) into internal RAM (which has limited capacity). The first-stage bootloader then initializes the DDR RAM and copies the second-stage bootloader (SSBL) from the SD card into DDR RAM. Finally it runs the SSBL. Our example apps are loaded by the SSBL.

Here's where the U-boot DDR driver code is: https://github.com/4ms/stm32mp1-baremetal/tree/master/third-party/u-boot/u-boot-stm32mp1-baremetal/drivers/ram/stm32mp1

Ps: you could technically run the MP1 without DDR RAM, and just run everything in SYSRAM and the other internal RAM sections...

Staringlizard commented 3 years ago

Thanks for clearing that out!