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Vivado Simulator v2021.2
Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
Running: /home/soc_qg/software/vitis2021.2/Vivado/2021.2/bin/unwrapped/lnx64.o/xelab --incr --relax --debug …
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Hi,
I am using the newest version of VsCode, hdl_checker-extension and hdl_checker-client. (Windows10)
As linter I use the ModelSim vcom.
It works good, while working on opened vscode and editi…
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Hello,
We have a client application using mariadb-connector/c 3.1.16 to connect to a MariaDB server (10.6).
We recently introduced proxySQL in the middle and since then we started to see the error…
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Thanks for the awesome configuration
I am a hardware engineer and I use too much of the VHDL and Verilog languages. Unfortunately, both are not supported by NeoVim built-in lsp. I find this language …
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### Is your feature request related to a problem? Please describe.
As of now mason-lspconfig doesn't allow to install LSPs for VHDL, a Hardware Description Languages.
### Describe the solution y…
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Would be nice to have a VHDL linter additionally.
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Are the cache.json files generated when using the LSP safe to publish to something like a public git repo?
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There is Xilinx IP that checks for violations of the AXI protocol on a bus: https://www.xilinx.com/products/intellectual-property/axi_protocol_checker.html
When designing a HDL core through SNAP it…
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how to configure Verilog/System Verilog to support in Emacs lsp-mode?
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suoto updated
4 years ago