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SPI BL702 - no "Byte-inverse signal for FIFO" option? **SPI_BYTE_MSB**
https://github.com/bouffalolab/bl_mcu_sdk/blob/master/drivers/lhal/include/bflb_spi.h#L66
BL702/704/706 Reference Manual:
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I am trying to use mfg_tool to generate partition binary but I am getting this error: ModuleNotFoundError: No module named 'esp_secure_cert'
I have also installed requirements.txt
![image](https…
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There is a header file "drivers/soc/bl808/std/include/bl808_ipc.h", but no implementations for these function in sdk.
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#### Problem
- Clone chip repo to depth 1
```
git clone --depth 1 https://github.com/project-chip/connectedhomeip.git /tmp/connectedhomeip
```
- Shallow clone the submodules with d…
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On Sipeed M1S Dock, when compiling for the BL808 D0 CPU none of the examples worked, JTAG revealed that the core was stuck in this IPC_SYNC loop: https://github.com/bouffalolab/bl_mcu_sdk/blob/9e189b6…
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Hi, I'm trying to understand how UART clock should be configured.
The reference manual clock diagram just shows one demux to select between `xclk`, `muxpll_160m_clk` and `mcu_bclk` and a divider:
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[CMSIS-SVD](https://www.keil.com/pack/doc/CMSIS/SVD/html/svd_Format_pg.html) files describe the register maps of the MCU, and are machine readable xml. There are automated tools, like [`svd2rust`](htt…
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There does not seem to be much in the way of documentation for using JTAG with the BL808 chip. I have been trying to use a RV Debugger Plus with a Ox64 board but am not able to examine any of the cor…
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Hi,
Just wondering why we are only allocating 64K DRAM in the D0 linker script when we have 512K?
https://github.com/bouffalolab/bl_mcu_sdk/blob/a574195a4b3399341794971a2ab4b8b17f4b70d7/bsp/board/…
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https://github.com/bouffalolab/bl_mcu_sdk/blob/16d3a819c86dab25e3c20155a3563c2dc9bc7220/bsp/board/bl808dk/bl808_flash_d0.ld#L25-L30
https://github.com/bouffalolab/bl_mcu_sdk/blob/16d3a819c86dab25e3…