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If a circuit environment STG is specified, then during simulation mark the input ports (e.g. by shading their names) that are enabled in the environment STG.
If simulation trace diverts from that …
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Please, in all components, add the option to restore default component parameters.
in this way I don't need to delete the component and re-add it in simulation.
Your application has the most poten…
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I was surprised to find out that the mnist example took in images (referred to as `x` in the `QFCModel` code) with a [256, 16] format, where 256 is the batch size and 16 is the shrunken then flattened…
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#code
from qiskit import *
from qiskit.circuit.library import *
from qiskit_aer import *
sim = AerSimulator(method='statevector', device='GPU')
qubits = 5
depth=2
shots = 5
circuit = Qua…
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The problem: Sonata specs force very complicated API to access reports.
When there is a report file, you want to open simply and access its data directly. Sonata specs, and hence bluepysnap, requir…
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This is a simple simulation of a mini circuits power splitter. You would expect there to be some small insertion loss between port 1 and ports 2&3 as well as a slight phase shift. However, the simulat…
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After some internal discussions, we see that we're frequently given a SONATA file in our apps (e.g.: Brayns) and we need to discover its type (usually either circuit or simulation config) by trying bo…
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I have a few simple enhancements which should really enhance the user experience for debugging large, latency sensitive circuits, such as CPUs. Microarchitecture is all about timings, after all.
S…
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I'm trying to create a timing diagram of a CPU whilst its executing a program, however it fails with the following error:
```
java.lang.ArrayIndexOutOfBoundsException: Index 2 out of bounds for leng…
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### Environment (OS, Python version, PySpice version, simulator)
Ubuntu 20.04.6 LTS
Python 3.8.10
PySpice version: '1.5'
Simulator: NGSpice
### Expected Behaviour
No error message ; elements v…