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There is a great tool by @snhobbs, that generates a testpoint report, cataloging all testpoints and a few useful bit of information about each.
https://github.com/snhobbs/kicad-testpoints
Test p…
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My circuit consists of many subcircuits that are in some library files. Can Align read these library files? If not, what can I do to make Align read the circuit and subcircuits at the same time? I don…
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How could we enable [SAX](https://flaport.github.io/sax/) simulations from QUCS?
@flaport
@nikosavola
![image](https://github.com/Qucs/qucs/assets/4514346/02dccd09-256b-421d-9f93-237965ac5f…
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Can we have a feature to flag abandoned projects? By abandoned I mean anything that haven't been updated in X years (1 or 2 for example).
This can be a valuable search filter as people would normal…
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Hi!
I am new to parsing and trying to learn by writing a spice netlist parser. In the first line of a spice netlist, there is an optional title string that gives the title to the circuit. How would…
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Sorry I don't have a better understanding of the error to give this issue a better name.
Example code is here:
https://github.com/rossc719g/bsc_examples/blob/main/internal_error_1/README.md
The…
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The temp_sensor in OpenFASoC has LVS issue after the update of write_cdl.
Link to OpenFASoC: (https://github.com/idea-fasoc/OpenFASOC)
The power nets in cdl file are unconnected.
![Capture](ht…
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I am experiencing an issue where any attempts to generate a Verilog for my test bench is segfaulting.
```
%> coreir --version
v0.1.51
```
This error can be reproduced by checking out `lake:sp…
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How can I use relative path for osdi shared libs?
![Bildschirmfoto vom 2024-04-19 20-44-48](https://github.com/ra3xdh/qucs_s/assets/18441932/3233df94-6eb2-4a16-b1aa-96a91da9c5d9)
The generated n…