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Is symbolator properly supported for verilog? I got the following error when I ran it on a .v file. I have tried out multiple output formats etc. but no joy.
``` sumanth@LAPTOP-MFGQBV4B:/mnt/g/sy…
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Some very useful LSP capabilities currently missing, are:
'textDocument/documentSymbol'
https://microsoft.github.io/language-server-protocol/specifications/specification-current/#textDocument_docu…
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Hey all,
I am working on controlling motors with a FPGA. You can see my working setup [here](https://youtu.be/-0uB2MydtrE) .
The video is not the greatest but it shows where I am at. Code for th…
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Hello Matthew,
I would like to ask, if you would be interested in a cooperation between your `pyucis` project and `pyEDAA.UCIS`, which is maintained by me and @umarcor. `pyEDAA.UCIS` is part of a s…
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status NEW severity *normal* in component *general* for *---*
Reported in version *1.5.6* on platform *Other*
Assigned to: Dimitri van Heesch
Original attachment names and IDs:
- _[Doxyfile](https://…
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When creating re-usable modules we create output signals, which quite often are not all used in an instantiation, and cause **undesirable warnings**.
In VHDL we have the _open_ keyword to tell the com…
josyb updated
7 years ago
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### Description
Select a data path row, then right click and get a menu to "Show in ..."
![image](https://user-images.githubusercontent.com/2798822/226295495-bf15596b-c2e1-41f1-8a9e-9141fc9f5596.p…
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For example,
```
config
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I more or less pushed all the remaining ctags parsers in the recent PRs so here's a short summary of the remaining diffs:
* geany_docbook.c: I think @masatake wanted to make this a proper XML parse…
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We have some places in our code where we hackishly/partially parse (parts of) SystemVerilog. It would be nice to choose an existing parser and integrate it properly into the codebase.
Currently we …