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When attempting to compile the current version of this PR: https://github.com/riscv/sail-riscv/pull/197 I get an error when compiling the C file generated by Sail:
```
make csim
gcc -g -I /mnt/rus…
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The following does not error or warn:
```
$ ./bin/clang /tmp/test.c -target riscv64 -march=rv32i -o - -S
```
And it produces code according to the value of `-march`:
```
.text
.…
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## Precommit CI Run information
Logs can be found in the associated Github Actions run: https://github.com/ewlu/gcc-precommit-ci/actions/runs/10786616991
## Patch information
Applied patches: 1 -> 1
A…
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# riscv特权级模型 | Sherlock's blog
本文分析riscv特权级spec,尝试依照spec总结下riscv的特权级模型。有时直接看 spec,可能过于分散,本文分析的时候结合qemu tcg riscv的代码。基于riscv的spec 是20190608,基于的qemu版本是5.1.50。
[http://wangzhou.github.io/riscv%E7%89%B9…
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需求:
1. 在 [2403_mugen失败测试用例清单](https://docs.qq.com/sheet/DSkZMUm9vSHFhTURL?tab=BB08J2) 中找到测试套 nftables 失败的测试用例
2. 在[openEuler RISC-V 24.03 版本](https://repo.tarsier-infra.isrc.ac.cn/openEuler-RISC-V…
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DV Bugs:
UVM_FATAL core_ibex_test_lib.sv(842) @ 8492700: reporter [uvm_test_top] Check failed dut_vif.dut_cb.priv_mode == mode (0 [0x0] vs 3 [0x3]) Incorrect privilege mode
I think a dv bug, spik…
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The code builds ok but it appears to crash immediately and `esptool monitor` throws an odd error:
```
podman run -it --rm -v /Users/bart/Code/riscv/mdk/examples/blinky:/Users/bart/Code/riscv/mdk/e…
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https://wiki.sipeed.com/hardware/en/lichee/th1520/lbook4a/lbook4a.html
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How to test the RISCV kernel developed with Verilog using rv32ui in riscv-tests?Thank you!
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This was requested by users, the monolithic way in which we generate the RiscV machine is a bit odd.
Our riscv implementation looks like
```
machine RiscV {
// implementation of riscv archi…