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**Is your feature request related to a problem? Please describe.**
no
**Describe the feature you'd like to see implemented**
on lower ecam fuel page fuel temperature for outer and inner …
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### Contact Details
_No response_
### Is your feature request related to a problem?
![image](https://github.com/user-attachments/assets/9e84d7ac-1c17-4ebe-a870-f22bce94e00c)
When exporting to js…
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Modern X86_64 CPUs have additional instruction sets to optimize certain operations. SIMD extensions like SSE4, AVX2, or AVX512 might speed up NumPy, SciPy, and PyTorch. CPU architecture since Intel Ne…
tiran updated
5 months ago
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Hi,
With default ISA (rv64imafdc), everything goes well.
But when I tried ISA=rv64imafdc_zba_zbb_zbs (RISC-V B BitManp standard extensions), many errors occur while building riscv64-unknown-linux…
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Recently I have a new cpu architecture other than the one listed, and build gives the following error:
```
# github.com/chewxy/math32
../../../../go/pkg/mod/github.com/chewxy/math32@v1.0.8/exp.go…
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Initial summary:
- ISA team to:
- review [ODIS documentation](https://book.oceaninfohub.org/)
- create an entry in [ODISCat](https://catalogue.odis.org)
- provide a draft of JSON-LD for one…
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[TurboBench](https://github.com/powturbo/TurboBench) : Build or download **[executables](https://github.com/powturbo/TurboBench/releases)** and test with your own data.
**Benchmark1:**
[TurboBench…
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### This issue is a place for discussions about newer unprivileged ISA extensions
Each extension should be evaluated for following qualities:
- Mandatory for a known usecase
- Benefit for guest (…
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Just capturing interest here to have Oaknut support more `ARMv_._` variations(maybe up to [ARMv8.6](https://en.wikipedia.org/wiki/AArch64#ARMv8.6-A_and_ARMv9.1-A)) and detection of some more of these …
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As a new custom $vocabulary extension, it would be useful to have the keyword `isa`, which would check that the indicated instance data is blessed into the indicated class. This isn't compatible with…