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The goal of UHDM is to allow "users" (like Yosys, Verilator and Icarus) of a SystemVerilog parsers not to care about the exact parser implementation. However, currently the only parser which exposes t…
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The following little script consume very much memory very fast due to a broken netlist. The netlist is parsed successfully but the attempt to display it seems to run into an infinite recursion.
(The …
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您好!我想使用你们开发的iEDA工具,但通过yosys生成的Netlist文件和sky130中的gcd.v文件格式不一致,调用iEDA命令运行会对always和assign语句报错,请问是有一些特殊的生成设置吗?
![image](https://github.com/OSCC-Project/iEDA/assets/103937567/fdadbdcd-5aad-4786-8647-636d0…
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May be related to #21 .
Using the base files for both Lucid and Verilog projects, `Build Project` fails:
```
Starting iceCube2...
C:\Program Files\Alchitry\Alchitry Labs>SET TCL_LIBRARY=C:\…
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### Summary:
I just noticed another issue with netlists, it demands to use the `a.b.c.d/y` form and does not accept forms like `a/y`, `a.b/y`, `a.b.c/y` which would be really nice to support also...
…
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In order to translate also to GDSFactory netlist format:
https://github.com/gdsfactory/gdsfactory/blob/main/gdsfactory/get_netlist.py
I am happy to do it if it would be accepted.
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Hello. I am running into a bug where function local variables are inferred as latches.
Version: 2023-10-11-ef5c0bb
Example:
```systemverilog
module latch_test (
input logic a,
outp…
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Would it be possible to add a new diagram type to design simple circuits such as this one:
It could be really useful.
Thanks in advance
Lorenzo
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For a new project, Verilator build phase is taking too long (more than 40 minutes which is 40 times longer than what I see on even driven simulators). This is quite unusual and contrasting with my pr…
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Putting the following example in the flow SV --> UHDM (w Surelog) --> Yosys (w f4pga plugin) --> SV shows that the following verilog with bit direction is incorrect:
Input:
```systemverilog
modul…