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The following snippet of code:
```
MOVE 0x0005, R1
MOVE 0x0007, R2
SUB R2, R1
```
calculates the subtraction 5-7 and gets the correct result -2 (represented as FFFE), but the overflow …
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* Save one CPU cycle for direct register "no frills" to register operations such as `MOVE R1, R2`, `ADD R3, R4`, `SHL R5, R6` etc.
* All these operations should be doable in 2 cycles instead of (l…
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The short program below leads to what I believe is incorrect assembly when compiled with optimizations (-O3).
The program is:
```
int a;
void f()
{
if (a < 2)
{
a=2;
…
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For 1.7 (or later): As described by Michael in issue #4 ISE vs. Vivado Riddle and #22 Refactor mmio_mux, the fact that we have this nice `inout` data bus plus the tristate buffers seem to be the reaso…
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Hello!
Could you please suggest which Xilinx FPGA I can use to implement this design for a UHS standard card?
Thank you!
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@MJoergen let's use this issue to get the refactored and much more elegant mmio_mux working.
Originally, there was pull request #16, but this lead to very strange behaviours of the keyboard. So I r…
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This needs to support what LÍ wants to do with RÁV, so:
- [x] Interpolating arbitrary variables to configurable height above ground.
- [x] Rotating wind vectors and speed from model directon to groun…