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Hi,
I have a layout which on viewing in magic didn't show any DRC errors (on the top right side of the window), but when I select the whole design and type `drc check`, then I can see there are some D…
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## Expected Behavior
N-tap and P-tap minimum area > 0.07011um^2
## Actual Behavior
N-tap and P-tap minimum area = 0.41 * 0.17 = 0.0697um^s
## Steps to Reproduce the Problem
run magic drc …
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CDL has parallel mos in series. layout has series mos in parallel. Logically equivalent, but not topologically equivalent.
https://skywater-pdk.slack.com/archives/C017UA7LEUV/p1604453653008500
## …
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## Expected Behavior
Capacitance data is available in the PDK ready to go with various tools.
There is some more information on the capacitance data under the [Parasitic Layout Extraction sectio…
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Hi,
I am trying to simulate the verilogA model - which open source tool(s) would you suggest to dump waveforms ?
Thanks
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The cell in question (`sky130_fd_sc_hd__clkdlyabuf4s15_1`) contains a poly overlap error (poly overlaps contact by 0.07um, where an overlap of 0.08um is required). There is no indication in the docum…
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All the diode_2 cell LEFs, such as at https://github.com/google/skywater-pdk-libs-sky130_fd_sc_hd/blob/master/cells/diode/sky130_fd_sc_hd__diode_2.magic.lef have a non-zero value for ANTENNAGATEAREA .…
tdene updated
3 years ago
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The Verilog-A model does a manual integration of the filament thickness here:
https://github.com/google/skywater-pdk-libs-sky130_fd_pr_reram/blob/6574676cbbd062d63be0f090013d59ced7302349/cells/rera…
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I was under the impression that conda-eda was usable from within conda, however it doesn't work, and there doesn't appear to be any documentation on how to use conda-eda under https://hdl.github.io/co…