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**Requirement:** Provide a language construct for conditional Wiring. This draws from the design of Chisel which uses "when" for conditional assignment, a convenient construct for defining control be…
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Here's an example:
```python
import magma as m
class Foo(m.Generator2):
def __init__(self, width):
self.io = m.IO(x=m.In(m.Bits[width]), y=m.Out(m.Bits[width]))
self.io.y…
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I tried creating an unrolled version of gaussian that uses unroll=4. However, there seems to be an issue with the unoptimized code. Specifically with the error below. The app is here: https://github.c…
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First of all, great project!
I am thinking of building a gate for myself, but I'm having a few issues:
"consist of 1 atmega16 for irda decoding/uart + 1 atmega328 for i2c/uart"
but I have found o…
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When we use `inline_verilog` for the verilog backend of the regfile, we produce verilog that has multiply driven nets:
```verilog
module my_regfile (
input ASYNCRESET,
input CLK,
inpu…
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I'm having trouble generating the unoptimized code for lucas_kanade. I encounter this error:
```
cd ./bin && LD_LIBRARY_PATH=/nobackup/setter/h2h/hwbuffer/polyir/../clockwork/lib:/nobackup/setter/h2…
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It won't map to CGRA if you disable the cgramapper pass. Shall we uncomment it?
https://github.com/dillonhuff/clockwork/blob/7862786af09848e1bc304838a30a0f644b12f28c/coreir_backend.cpp#L2260
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The desired use case is generating a design where all the relevant verilog modules have a specific prefix (this is used to distinguish the design components from others when integrated in a larger des…
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Right now, magma takes the first clock driver it finds in the interface and uses it as the automatic driver for unwired clocks. The proposal is to raise an error if there is more than one possible de…
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I am refactoring my shift-register optimization pass. (`generate_bank_and_merge`, `port_group_banks`)
Eventually the difference between single port mem and dual port is just the bank grouping.
I am …