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## Problem
There is no Major for any HDL(Hardware Description Language)s as I see it.
Like VHDL, Verilog and SystemVerilog.
## Solution
Implement Major modes for HDLs?
## Alternatives
Develo…
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**Describe the enhancement**
Support using a login shell along with the container step syntax.
**Code Snippet**
```yml
# Produces an error
Action_String:
needs: Image
runs-on:…
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With pptrees v1.2.6
I have a simple script:
```
from pptrees.YosysAdder import YosysAdder as forest
width = 9
f = forest(width, alias = "sklansky")
f.hdl('adder.v')
```
This gives the fo…
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### Answers checklist.
- [X] I have read the documentation [ESP-IDF Programming Guide](https://docs.espressif.com/projects/esp-idf/en/latest/) and the issue is not addressed there.
- [X] I have updat…
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When exporting to VHDL, all registers are uninitialized. When creating a circuit with feedback from flip-flops or using counters without connecting the load input, there's no way to get into a defined…
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If one writes `nameHint (SSym @"hi") ...` there is a good chance that GHC's `unpack` rewrite rule will rewrite the `String` in the term-level evidence carried by `SSym` (which is the only thing preser…
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When withdrawing an item the system should
- ask for the withdrawal reason
- store the reason in provenance
- store the reason in local.withdrawn.reason
- in some cases display the reason on a t…
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I think it would be a nice idea to add the possibility to export to HDL from the CLI. It would allow the integration of Digital in Makefile or build scripts.
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One thing that would help me (and possibly others) get up to spee quickly would be if I could use the same source command file that I use for icarus and verilator (arguably the two most popular open s…