-
## Support Question
Hello,
We are exploring the implementation of FDC3 to enable communication between our custom desktop applications (Windows .NET-based), custom web-based applications (typicall…
-
GT40; SW 1
GT40; SW BIN
GT40; SW P11
SW P11 is an E text file. "COPYRIGHT 1973 by Botond G. Eross". Stanford A. I. Project, August-September 1973. SW 1 is a SAILV'ed version, or at least t…
-
https://github.com/proboston/sails-fixtures/blob/a20e0d7ca837178e68830d388512e3a9c813f0f6/lib/index.js#L164
with models.migrate === 'safe' || 'drop' I get the following message when the existing da…
-
**Node version**: 14.20
**Sails version** _(sails)_: 1.2.3
**ORM hook version** _(sails-hook-orm)_: 2.1.11
**Sockets hook version** _(sails-hook-sockets)_: 2.0.0
**DB adapter & version** _(e.g. sa…
-
We are using zephyr V3.6.0 and SDK version 0.16.5-1.
We are written code for Uart HW DMA for STM32H743 controller.
Assuming a buffer of 256 Bytes, A message sent with 257 bytes will cause an overflo…
-
**Sails version**: 1.0
**Node version**: 8.10.0
**NPM version**: 5.0.4
**DB adapter name**: postgres
**DB adapter version**: N/A
**Operating system**: Windows10
Hi,
A lot of h…
-
When building rmem from scratch, it pulls sail from our local repos https://github.com/rems-project/opam-repository/tree/opam2/packages/sail
If it pulls sail=0.13 then a problem can happen, because…
-
If a few pipelines are failing, there is no way for us to re-test only the failed ones.
Restarting all of them is a waste of resources and increases the chance of getting transient errors on pipel…
-
The ARM model contains calls to a number of extra primitives that we don't implement yet:
```
arith_shiftr: (%bv, %i) -> %bv
set_slice_int: (%i, %i, %i, %bv) -> %i
undefined_int: (%unit) -> …
-
Hi there,
I've identified an issue related to the Sail-to-SystemVerilog translator. The problem arises when translating Sail code that involves the `foreach` construct.
Simply put, I suspect that …