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Hi,
I have a project involving image processing and neural networks which I want to port to Xilinx platform zcu104_rv_ss. It was made using LeNet and I have successfully got the executable file for t…
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I built the ```parallel_accel``` example for my zedboard and noticed it did not produce any performance gain over the software implementation:
```
root@avnet-digilent-zedboard-2017_2:/mnt# ./run.elf…
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I tried to compile by specifying platform to microzed. But several errors came out like:
`This design requires 28666 of such cell types but only 17600 compatible sites are available in the target …
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I have built the hardware and sofrware code with Xilinx SDx 2018.2 tools successfully. But when I run the GoogleNet with 6-bit weights on ZCU102, the fps can only achieve 33.5, instead of the 220 fps…
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I ran chaidnn using the zcu102 board.
For larger data, I'm trying to use an SSD, but the board does not recognize nvme.
I have verified that the lspci command recognizes ssd, but there is no nvme in…
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Hi, I'm new to PYNQ and I'm trying to understand the architecture about PYNQ Linux drivers. But I can't understand why they can bypass Linux kernel and directly operate hardware registers.
From the…
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Xilinx tools (SDAccel, SDSoC, HLS...) provide extensions to express pipelining, dataflow, partitionning,
https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_2/ug1023-sdaccel-user-guid…
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Hi @changwoolee ，I‘m VERY interested in your project, you've got a brilliant acheivement.
I also got a zynq-7020 board. But I am a newcomer in this area.
May you tell me how to run your projcet on t…
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when I make sdsoc_build to generate FPGA bitstream.
One error has happened:
INFO: [SDSoC 0-0] Performing accelerator source linting for top
INFO: [SDSoC 0-0] Moving function top to Programmable …
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When I run `make -j4` on the fpga bitstream I keep getting this build error. Anyone ever run into this?
![sds](https://user-images.githubusercontent.com/11166304/37868398-07638746-2f7c-11e8-8050-a770…