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We currently define hierarchy paths using SV macros at the chip and block-level. Ideally, the block-level include files should be reusable in the chip-level environment.
However, due to the way the…
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The way the wrapper scripts are, it's not possible to call the scripts without setting an environment variable as the Toplevel name that ends generating the output binary and header.
The ideal way …
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The idea is to plot a dependency graph for the given core/system
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Add support for getting the provider from an external file (e.g. fusesoc.provider in the library root). This would allow using the same .core file for local and remote cores
olofk updated
3 years ago
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I've recently found it useful to be able to be able to query the dependencies of all the core files in libraries known to fusesoc. My use case is that I am making a breaking change to a low level core…
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Please add a mechanism to specify a branch/tag name and additional options like '--depth' to a library's git URI.
For repositories that are large, with many branches and tags, without such a mechanis…
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Since d8ece6b5 file names in filesets can contain environment variables, which are expanded during parsing. I'd like to better understand the use case for this feature, and potentially get rid of it.
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Hi
when the flow was compiling the RTL files, the following issue popped up:
![1668577295854](https://user-images.githubusercontent.com/30075118/202093380-d97cec6b-6330-4fe5-a826-12d71ad993b2.png…
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There are many use cases for opening a EDA tool in interactive mode. FuseSoC should make this easy by adding a command-line switch or similar to open a tool in interactive mode after configuration, bu…
olofk updated
3 years ago
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I'm trying to add my board[ opos6ul_sp in the corescore project.](https://github.com/Martoni/corescore/commit/29af1313cc7e7f0842cfce885bacbe6f50cd98b0) but I'm stuck with a $clog2() problem.
```
ERR…