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()
{}
[]
Reported on discordbot by discord user
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InvalidDataException
We think we should have set eld but it's not in…
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#### Description of Bug:
When trying to run the script:
`python3 -m mtgjson4 -ac`
It fails with 'forbidden' with the following output:
```
[INFO] 2019-06-13 08:41:30,510: Fetching from Sc…
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My observation when running code that uses PMP on the HiFive Unleashed board is that, if an access results in a page fault that resolves to a superpage, PMP checks are performed for the entire extent …
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- [Yes.] I carefully read the [contribution guidelines](https://github.com/TeamNewPipe/NewPipe/blob/HEAD/.github/CONTRIBUTING.md) and agree to them.
- [Yes.] I checked if the issue/feature exists in …
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Hello,
I have some questions and observations about memory support on RISCV architectures: specifically, I'm seeing two odd behaviors because of the way some features have been defined, and I want …
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I already posted it to the group but I think it might be better to have an issue here for tracking as well. The current ASID design suggests that ASID are local to each harts, which could severely pen…
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We want to change BP mem to 1) read in from plusargs instead of boot rom and 2) support more than 15 bit addresses. When we run larger benchmarks, this could become an aliasing issue.
Outside of b…
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"As noted on isa-dev, we forgot to write down the interaction between
PMPs and TLBs. The idea is that VA->PA mappings can be cached, and
the PMP access can occur any time between the page-table wal…
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- [x] Add tests to individual functions.
- [x] Improve the documentation. (Right now, the individual functions are documented but the big picture needs to be added describing what are the main funct…
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In the current spec, from what I understand so far:
- writes to `pte`s in memory need to be synchronized with `sfence.vma`
- writes to `pmp` csrs need to be synchronized with `sfence.vma`
- write…