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I've got a weird case where it is not possible to continue routing a BRAM output net (in this case DOADO[0] on an xc7a200t). I do require a custom router for my application, so I followed the [RapidWr…
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See SymbiFlow/fpga-interchange-schema#42 for more background
At the moment, the way that parameters are split up for primitives like distributed RAM and `LUT6_2` is not output into the resources.
…
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Vivado has a `OBUFDS_DUAL_BUF` macro for pseudo-differential, non-tristate, differential outputs:
![Screenshot from 2021-07-27 11-54-37](https://user-images.githubusercontent.com/78621419/127142549…
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Run
```
./scripts/invoke_rapidwright.sh com.xilinx.rapidwright.interchange.DeviceResourcesExample xczu3eg-sbva484-1-i
```
fails with
```
Exception in thread "main" java.lang.RuntimeException…
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See the discussion in SymbiFlow/fpga-interchange-schema#40 and SymbiFlow/fpga-interchange-tests#42
Currently a single entry is hard-coded in the macro expansion map: https://github.com/Xilinx/Rapid…
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Track the issue SymbiFlow/fpga-interchange-tests#40. The goal is to provide cell pin default connections for a new instance.
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On the latest version of RapidWright, I encounter this exception whenever EDIFNetlist.generateParentNetMap() is used on a flat design that has the hiearchy separator ('/') in cell and/or net names. Ob…
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Device resources stored using the FPGA interchange format for any 7-series FPGA are missing definition of the `OBUFDS_DUAL_BUF` macro in the macro library. This prevents nextpnr from correctly expandi…
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Hi!
It would be great if instead of this:
```
Exception in thread "main" java.lang.ExceptionInInitializerError
at com.xilinx.rapidwright.design.Design.setPartName(Unknown Source)
at com.xil…
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Not sure if I'm doing something wrong, as I'm surprised this hasn't been hit by someone else yet?
Consider:
```java
package net.gatecat.fpga;
import java.io.File;
import java.io.IOException…