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A fresh issue for one of the two boards proposed in [[RFC] Sinara Servo sinara-hw/meta#16](https://github.com/sinara-hw/meta/issues/16).
This would be a high performance board using the FPGA on a K…
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- [x] DNP JESD204 ADC on Sayma RTM, as well as all associated components (regulators etc). Do not remove from schematic/PCB, so that users can populate them if they desire.
- [x] If easily possible, …
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Test setup:
- using ADF4356 eval board
- clock applied single-ended to REFINA SMA at +6dBm
- cut traces to disconnect on board XO from PLL ref in
- remove R7 to power down XO
- replace R6…
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Analog Devices has come out with a new set of chips (AD916x) which support output update rates of 12 GSPS, with instantaneous bandwidths of >1 GHz and a variety of interpolation factors. These are su…
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In Sayma v1 Ethernet is complicated by support for both MMC uP and FPGA. Happily this is now working but it could be made simpler. A low risk simplification is to abandon Ethernet support for MMC and …
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I haven't figured out the exact sequence of events, but here is a rough observation about the HMC830:
- it is possible to make it go into lockups where it does not lock. It identifies correctly and t…
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I've been thinking a bit more about what Sayma v2.0 should look like, and I want to raise the possibility of dropping support for the low-level RF backplane.
My proposal is that we drop support fo…