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Is there a way I can reinterpret a fixed point number with different number of fractional bits?
In my use case I'm receiving MyHDL intbv objects which are actually fixed-point values with some fra…
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I have a myhdl background and maybe that's why this seems like a very easy task to me.
in myhdl you can define a elaboratele thing like this (http://docs.myhdl.org/en/latest/manual/reference.html#m…
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The MLIR python [bindings documentation](https://mlir.llvm.org/docs/Bindings/Python/) make bindings to Python sound easy to set up, though somehow I suspect differently. @GeorgeLyon are you working on…
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Dave,
tried to start using your pygmyhdl. did a pip install of it and got the following
```
from pygmyhdl import *
---------------------------------------------------------------------------
…
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I think there is a really neat workflow in which the test bench is defined using cocotb, and the code is written in MyHDL with continuous verification using cocotb. The generated VHDL/Verilog can then…
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Summary
A few links in the "What's new in MYHDL 0.8" and "What's new in MYHDL 0.7" point to old links of the form: http://www.myhdl.org/doku.php/meps:mep-108 . They should instead be pointing to:…
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Hi, I'm new to Python, so forgive me if I'm not seeing something basic. When I try to run the script, this is the output. I have python 3.9 and myHDL 0.11.0 installed. Please advise. Thanks!
C:…
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@eine I'm trying to add an ECP5 PLL to microwatt and looking at https://github.com/ghdl/ghdl-yosys-plugin/blob/master/examples/ecp5_versa/Makefile it seems I need components.vhdl from there to be able…
mikey updated
3 years ago
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Is there any similar syntax in myhdl like **parameter** in verilog?
(e.g. **#( parameter N = 8)**)
I want it applied when I convert myhdl code to verilog code.
Examples:
```
module dff #( par…
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File: pyfda/hdl_generation/hdl_specs.py
Since integrating the SOS (second-order sections) from scipy.signal, the designed filter can be retrieved in SOS format from the central dict via
`fb.fil[0]['…