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Hello,
I have changed the device "LFE5U-12F" to "LFE5U-25F" in cynthion_r1_4.py, set the system variable LUNA_PLATFORM ="cynthion.gateware.platform:CynthionPlatformRev1D4", and have a dry run like…
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In https://github.com/apfelaudio/tiliqua/pull/38, I modified a whole bunch of things to add support for the -25K LUT SC variant. This included modifying the PLL configuration to use 2 PLLs instead of …
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We want examples that:
- have comments not at top of file
- have processes that get evaluated
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Right now it is only documented in my head, which is suboptimal.
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* RFC PR: https://github.com/amaranth-lang/rfcs/pull/36
* Implementation PR: https://github.com/amaranth-lang/amaranth/pull/1344
* Documentation PR: https://github.com/amaranth-lang/amaranth/pull/13…
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When awaiting a TriggerCombination that waits for both a delay() to expire and a signal to change, if the delay expires at the same time as when the signal changes, BrokenTrigger is thrown.
Here is m…
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It would be useful to have some guidance on preferred usage of the project's new name.
The full title of the project is now "Amaranth HDL", but in most instances within the documentation it is refe…
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I'm using Amaranth for university classes, where the students have access to DE1-SoC and DE2-115 boards. The board definition for DE1-SoC in `amaranth-boards` is very incomplete, and there is no defin…
tilk updated
10 months ago
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External memory comes out of reset full of garbage. In cases where we have no SoC initializing the external memory, this means any `DelayLine` instance backed by external memory will emit garbage for …
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You get messages like:
```
amaranth.hdl._ir.DriverConflict: Bit 0 of I/O port (io-port port_a_5__io__io) used twice, at /home/whitequark/Projects/glasgow/software/.venv/lib/python3.12/site-package…