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This test program:
``` python
import myhdl
from myhdl import ResetSignal, TristateSignal, Signal, always_seq, instances
@myhdl.block
def test_bench():
clock = Signal(bool())
reset = ResetSig…
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I'd like to use an 2D arrays port:
output [7:0] data_out[0:3];
Is there any example for generating such port definition in myhdl?
--------------------------------------------------------------…
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MyHDL code below:
```
#!/usr/bin/env python
from myhdl import *
MAX = 16
def myhdl_b1(i, o):
c = intbv(4,min=0,max=MAX)
@always_comb
def rtl():
o.next = i + c
return rtl
i, o = [Sig…
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Tristate Signals are unconvertable in @always_seq blocks with resets. (This happens with the current tip)
The following code generates a conversion error when the reset parameter to always_seq() is t…
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Hi All, I was recently playing with cosimulation on windows 10 and noted that the pipe communication between myhdl.vpi and myhdl doesnt work. Actually this was somewhat noticed by a broken testcase in…
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i had problems to get my code, that was running on one computer with python3.8, running on an other with python3.11. there were many strage messages, pointing deep in myHDLs verilog-converter. i neede…
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When I try to build any of the projects in this repository, I get the following traceback.
Traceback (most recent call last):
File "project1.py", line 139, in
run()
File "/home/kg6hum/dcc201…
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I'm convinced that I want to learn MyHDL (or least play with it for a couple hours).
It would be awesome if there was a plain-and-simple Getting Started page which explains some basic concepts, exp…
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Pip 1.5 does not process dependency links by default anymore(pypa/pip#1428), and MyHDL on pip is too old.
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First day with MyHdl. I'm using Anaconda (Python 3.x) under Windows. Installed MyHdl with pip. Went to run the "Hello World" example in the manual and got:
from myhdl import block, instance, d…